er.vhd

初学ＶＨＤＬ有用的

library ieee;
use ieee.std_logic_1164.all;
use work.mypack1.all;
entity er  is
port(a,b:in std_logic;
      q:out std_logic);
end er;
architecture behav of er is
begin
q<=minium(a,b);
end;