bb.vhd

来自「初学ＶＨＤＬ有用的」· VHDL 代码 · 共 14 行

ENTITY bb IS
		PORT(
		d0, d1: IN	BIT;
		sel: IN	BIT;
		q: OUT	BIT);
END BB
;
ARCHITECTURE dataflow OF bb IS
	BEGIN
	q<=(d0 AND sel )OR(not sel and d1);
	END dataflow;