bin.vhd

初学ＶＨＤＬ有用的

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity BIN is
port(B:in std_logic_vector(3 downto 0);
     en:in std_logic;
     G:out std_logic_vector(3 downto 0));
end BIN;

architecture GRAY of BIN is
begin
PROCESS(B,EN)
BEGIN
IF(EN='1') THEN
   CASE B IS  
   WHEN "0000"=>G<="0000";--0 --0
   WHEN "0001"=>G<="0001";--1 --1
   WHEN "0011"=>G<="0010";--2 --3
   WHEN "0010"=>G<="0011";--3 --2
   WHEN "0110"=>G<="0100";--4 --6
   WHEN "0111"=>G<="0101";--5 --7
   WHEN "0101"=>G<="0110";--6 --5
   WHEN "0100"=>G<="0111";--7 --4
   WHEN "1100"=>G<="1000";--8 --12
   WHEN "1101"=>G<="1001";--9 --13
   WHEN "1111"=>G<="1010";--10 --15
   WHEN "1110"=>G<="1011";--11 --14
   WHEN "1010"=>G<="1100";--12 --10
   WHEN "1011"=>G<="1101";--13 --11
   WHEN "1001"=>G<="1110";--14 --9
   WHEN "1000"=>G<="1111";--15 --8 
   WHEN OTHERS=>G<="XXXX";
END CASE;
ELSE
   G<="0000";
END IF;
END PROCESS;
end GRAY;