d.vhd

初学ＶＨＤＬ有用的

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY D IS
	PORT
	(	D,CLK: IN	std_logic;
		Q: OUT std_logic);	
END D;

ARCHITECTURE behave OF D IS
BEGIN
PROCESS(CLK)
BEGIN
   IF(CLK'EVENT AND CLK='1')THEN
       Q<=D;
   END IF;
END PROCESS;
END behave;