mux1.vhd

初学ＶＨＤＬ有用的

library ieee;
use ieee.std_logic_1164.all;   --库定义                                 
--*************************
ENTITY mux1 IS
PORT(
 d0,d1,sel : IN	bit;
   q	: out	bit);
END mux1 ;                             --端口定义     
--************************************
ARCHITECTURE example OF mux1  IS
BEGIN
   signal tmp1,tmp2,tmp3: bit;                 
begin
  block
   begin
    tmp1<=d0 and sel;
    tmp2<=d1 and (not sel);
    tmp3<=tmp1 or tmp2;
    q<=tmp3;
  end block;
 end example;