and.vhd

初学ＶＨＤＬ有用的

LIBRARY IEEE;
USE IEEE.STD_LOGIC.ALL;
ENTITY mux IS
	GENERIC(m: TIME:=  1ns);
	PORT(
		d0, d1,sel: IN	BIT;
		q	: OUT	BIT);
END mux;
ARCHITECTURE connect OF mux IS
	SIGNAL tmp: BIT;
BEGIN
	cale:  Process (d0,d1,sel)

	VARIABLE tmp1,tmp2,tmp3: BIT;
		BEGIN
		  tmp1:=d0 AND SEL;
		tmp2:=d1 AND (NOT sel)	
		tmp3:=tmp1 OR tmp2;	
		tmp<=tmp3;
          q<=tmp AFTER m	
			END PROCESS ;
	END connect;