counter241.vhd

初学ＶＨＤＬ有用的

--******************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--******************************************************

ENTITY COUNTER241 IS
	PORT(
			CP 	 : IN  STD_LOGIC;			--时钟脉冲   
			CLR  : IN  STD_LOGIC;				--清除信号    
			EC   : IN  STD_LOGIC;				--使能计数信号 
            bcdg: out std_logic_vector(3 downto 0);
            bcds: out std_logic_vector(3 downto 0);  
			CY24 : OUT STD_LOGIC				--计数24进位信号        
		);
END COUNTER241;

--*******************************************************

ARCHITECTURE a OF COUNTER241 IS
	SIGNAL Q : STD_LOGIC_VECTOR (4 DOWNTO 0) ;
	SIGNAL RST, DLY : STD_LOGIC;
    signal bcd :std_logic_vector(7 downto 0);
BEGIN
	PROCESS (CP,RST)			-- 计数24     
	BEGIN
		IF RST = '1' THEN
			Q <= "00000";			-- 复位计数器  
		ELSIF CP'event AND CP = '1' THEN
			DLY <= Q(4);
			IF EC = '1' THEN
				Q <= Q+1;			-- 计数值加1    
			END IF; 			
		END IF;
	END PROCESS;
    bcdg<=bcd(3 downto 0);
    bcds<=bcd(7 downto 4);
  	CY24 <= NOT Q(4) AND DLY;				-- 进位信号微分       
	RST <= '1' WHEN Q=24 OR CLR='1' ELSE	-- 复位信号设定       
		   '0';
Binary_BCD : Block
BEGIN
	BCD <=	"00000000" WHEN q = 0 ELSE
			"00000001" WHEN q = 1 ELSE
			"00000010" WHEN q = 2 ELSE
			"00000011" WHEN q = 3 ELSE
			"00000100" WHEN q = 4 ELSE
			"00000101" WHEN q = 5 ELSE
			"00000110" WHEN q = 6 ELSE
			"00000111" WHEN q = 7 ELSE
			"00001000" WHEN q = 8 ELSE
			"00001001" WHEN q = 9 ELSE
			"00010000" WHEN q = 10 ELSE
			"00010001" WHEN q = 11 ELSE
			"00010010" WHEN q = 12 ELSE
			"00010011" WHEN q = 13 ELSE
			"00010100" WHEN q = 14 ELSE
			"00010101" WHEN q = 15 ELSE
			"00010110" WHEN q = 16 ELSE
			"00010111" WHEN q = 17 ELSE
			"00011000" WHEN q = 18 ELSE
			"00011001" WHEN q = 19 ELSE
			"00100000" WHEN q = 20 ELSE
			"00100001" WHEN q = 21 ELSE
			"00100010" WHEN q = 22 ELSE
			"00100011" WHEN q = 23 ELSE
			"00000000";
END Block Binary_BCD;
	END a;