pluse.vhd

初学ＶＨＤＬ有用的

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pluse is
port (data : in std_logic_vector(7 downto 0);
      start,clk : in std_logic;
      light : out std_logic;       
        q0,q1 : out  std_logic_vector(7 downto 0));
end pluse;
ARCHITECTURE aaa OF pluse IS
signal count2 :std_logic_vector (7 downto 0);
signal clkin:std_logic;

begin

process(clk,start)
 variable count :std_logic_vector (7 downto 0);
begin
if start='0' then
	count:=data+1;
elsif (clk'event and clk='1') then
	if count="00000000" then count:=count;
	else count:=count-1; end if;

if ((count(3)='1') and ((count(2)='1') or (count(1)='1'))) then
count:=count-6;
end if;
if ((count(7)='1') and ((count(6)='1') or (count(5)='1'))) then
count:="00000000";
end if;
count2<=count;
end if;

end process;
clkin<='0' when (start='1' and  count2="00000000" ) or start='0' else
 		clk ;
q0<=count2;
light<=clkin;
process(clk)
 variable count1 :std_logic_vector (7 downto 0);
begin
if start='0' then
	count1:="00000000";
elsif (clk'event and clk='0') then
	if clkin='1' then 
	 count1:=count1+1;end if; 

if ((count1(3)='1') and ((count1(2)='1') or (count1(1)='1'))) then
count1:=count1+6;
end if;
if ((count1(7)='1') and ((count1(6)='1') or (count1(5)='1'))) then
count1:="00000000";
end if;
q1<=count1;

end if;

end process;


END aaa;