and2_2.vhd

初学ＶＨＤＬ有用的

--与非门的结构描述          

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2_2 IS
		PORT(
		a,b: IN	bit;
				y: OUT	bit);
END ;
ARCHITECTURE struct OF and2_2 IS
component inv_comp
     port(a:in bit;
           c:out bit);
     end component;
component and2_comp
     port(a,b:in bit;
           c:out bit);
     end component;
signal out1:bit;
begin
    u1:and2_comp port map(a,b,out1);
    u2:inv_comp port map(out1,y);	
END struct;