count60m.vhd

初学ＶＨＤＬ有用的

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--****************************
entity count60m is
port(
    rcos:in std_logic;
    resetm:in std_logic; 
    chem:in std_logic;
    rcom:out std_logic;
     qh,ql:buffer std_logic_vector(3 downto 0)
   );
end count60m;
--******************************
architecture datablow of count60m is
begin
process(rcos,chem,resetm)
begin
wait until(rcos'event and rcos='1');
if chem='1'then
ql<=ql+1;
end if;
if resetm='1'or (qh="0101"and ql="1001")then
qh<="0000";
ql<="0000";
rcom<='1';
else
if ql="1001"then
ql<="0000";
qh<=qh+1;
if qh="0101"then
qh<="0000";
else
qh<=qh+1;
end if;
else
ql<=ql+1;
end if;
rcom<='0';
end if;
end process;
end datablow;