avr_core.vhd

一个FPGA的AVR_Core 仅供测试~

              alu_z_flag_out => sg_alu_z_flag_out,
              alu_n_flag_out => sg_alu_n_flag_out,
              alu_v_flag_out => sg_alu_v_flag_out,
              alu_s_flag_out => sg_alu_s_flag_out,
              alu_h_flag_out => sg_alu_h_flag_out,

-- *********************************************************************************************
-- ******************** INTERFACES TO THE GENERAL PURPOSE REGISTER FILE ************************
-- *********************************************************************************************
          reg_rd_in   => sg_reg_rd_in,
          reg_rd_out  => sg_reg_rd_out,
          reg_rd_adr  => sg_reg_rd_adr,
          reg_rr_out  => sg_reg_rr_out,
          reg_rr_adr  => sg_reg_rr_adr,
          reg_rd_wr   => sg_reg_rd_wr,

          post_inc    => sg_post_inc,
          pre_dec     => sg_pre_dec,
          reg_h_wr    => sg_reg_h_wr,
          reg_h_out   => sg_reg_h_out,
          reg_h_adr   => sg_reg_h_adr,
   		  reg_z_out   => sg_reg_z_out,

-- *********************************************************************************************
-- ******************** INTERFACES TO THE INPUT/OUTPUT REGISTER FILE ***************************
-- *********************************************************************************************

          sreg_fl_in    => sg_sreg_fl_in, --??   
          sreg_out      => sg_sreg_out,    

          sreg_fl_wr_en => sg_sreg_fl_wr_en,

          spl_out       => sg_spl_out,       
          sph_out       => sg_sph_out,       
          sp_ndown_up   => sg_sp_ndown_up,
          sp_en         => sg_sp_en,
  
          rampz_out     => sg_rampz_out,

-- *********************************************************************************************
-- ******************** INTERFACES TO THE INPUT/OUTPUT ADDRESS DECODER  ************************
-- *********************************************************************************************
          
--		  ram_data_in  : in std_logic_vector (7 downto 0);
--          adr          : in std_logic_vector(5 downto 0);         
--          iore         : in std_logic;       -- CORE SIGNAL         
--          ramre        : in std_logic;	   -- CORE SIGNAL         
--          dbusin       : out std_logic_vector(7 downto 0));	-- CORE SIGNAL         			 

-- *********************************************************************************************
-- ******************** INTERFACES TO THE BIT PROCESSOR   **************************************
-- *********************************************************************************************

              bit_num_r_io    => sg_bit_num_r_io,  
              bitpr_io_out    => sg_bitpr_io_out, 

              branch     => sg_branch, 

              bit_pr_sreg_out => sg_bit_pr_sreg_out,

              sreg_bit_num    => sg_sreg_bit_num, 

              bld_op_out      => sg_bld_op_out, 

              bit_test_op_out => sg_bit_test_op_out,


-- OPERATION SIGNALS INPUTS

              -- INSTRUCTUIONS AND STATES

              idc_sbi_out  => sg_idc_sbi,
              sbi_st_out   => sg_sbi_st,
              idc_cbi_out  => sg_idc_cbi,
              cbi_st_out   => sg_cbi_st,

              idc_bld_out  => sg_idc_bld,
              idc_bst_out  => sg_idc_bst,
              idc_bset_out => sg_idc_bset,
              idc_bclr_out => sg_idc_bclr,

              idc_sbic_out => sg_idc_sbic,
              idc_sbis_out => sg_idc_sbis,
              
              idc_sbrs_out => sg_idc_sbrs,
              idc_sbrc_out => sg_idc_sbrc,
              
              idc_brbs_out => sg_idc_brbs,
              idc_brbc_out => sg_idc_brbc,

              idc_reti_out => sg_idc_reti
				 
);




general_purpose_register_file: component reg_file 
		  generic map(ResetRegFile => TRUE)
	      port map (
          reg_rd_in   => sg_reg_rd_in,
          reg_rd_out  => sg_reg_rd_out,
          reg_rd_adr  => sg_reg_rd_adr,
          reg_rr_out  => sg_reg_rr_out,
          reg_rr_adr  => sg_reg_rr_adr,
          reg_rd_wr   => sg_reg_rd_wr,

          post_inc    => sg_post_inc,
          pre_dec     => sg_pre_dec,
          reg_h_wr    => sg_reg_h_wr,
          reg_h_out   => sg_reg_h_out,
          reg_h_adr   => sg_reg_h_adr,
   		  reg_z_out   => sg_reg_z_out,

          clk  => cp2,       
          nrst => ireset      

 );


bit_proc: component bit_processor port map(
  
              clk   => cp2,                   
              nrst => ireset,                  
              
              bit_num_r_io  => sg_bit_num_r_io,  
              dbusin        => sg_dbusin,   
              bitpr_io_out  => sg_bitpr_io_out,   

              sreg_out      => sg_sreg_out,   
              branch   => sg_branch,  

              bit_pr_sreg_out => sg_bit_pr_sreg_out,

              sreg_bit_num    => sg_sreg_bit_num,

              bld_op_out      => sg_bld_op_out,
              reg_rd_out      => sg_reg_rd_out,

              bit_test_op_out => sg_bit_test_op_out,


-- OPERATION SIGNALS INPUTS

              -- INSTRUCTUIONS AND STATES

              idc_sbi  => sg_idc_sbi,        
              sbi_st   => sg_sbi_st,       
              idc_cbi  => sg_idc_cbi,       
              cbi_st   => sg_cbi_st,       

              idc_bld  => sg_idc_bld,       
              idc_bst  => sg_idc_bst,       
              idc_bset => sg_idc_bset,       
              idc_bclr => sg_idc_bclr,       

              idc_sbic => sg_idc_sbic,       
              idc_sbis => sg_idc_sbis,       
              
              idc_sbrs => sg_idc_sbrs,        
              idc_sbrc => sg_idc_sbrc,        
              
              idc_brbs => sg_idc_brbs,        
              idc_brbc => sg_idc_brbc,        

              idc_reti => sg_idc_reti
);                      


io_dec:component io_adr_dec port map (
          adr          => sg_adr,
          iore         => sg_iore,
          dbusin_int   => sg_dbusin,			-- LOCAL DATA BUS OUTPUT
          dbusin_ext   => dbusin,               -- EXTERNAL DATA BUS INPUT
                   
          spl_out      => sg_spl_out,
          sph_out      => sg_sph_out,
          sreg_out     => sg_sreg_out,
          rampz_out    => sg_rampz_out
);

io_registers: component io_reg_file port map (
          clk        => cp2,
          nrst       => ireset,     

          adr        => sg_adr,       
          iowe       => sg_iowe,
          dbusout    => sg_dbusout,     

          sreg_fl_in => sg_sreg_fl_in,
          sreg_out   => sg_sreg_out,

          sreg_fl_wr_en => sg_sreg_fl_wr_en,

          spl_out  => sg_spl_out,    
          sph_out  => sg_sph_out,    
          sp_ndown_up => sg_sp_ndown_up, 
          sp_en     => sg_sp_en,   
  
          rampz_out => sg_rampz_out   
);



ALU:component alu_avr port map(

              alu_data_r_in => sg_alu_data_r_in,
              alu_data_d_in => sg_alu_data_d_in,
              
              alu_c_flag_in => sg_sreg_out(0),
              alu_z_flag_in => sg_sreg_out(1),


-- OPERATION SIGNALS INPUTS
              idc_add  => sg_idc_add,
              idc_adc  => sg_idc_adc,      
              idc_adiw => sg_idc_adiw,     
              idc_sub  => sg_idc_sub,     
              idc_subi => sg_idc_subi,     
              idc_sbc  => sg_idc_sbc,     
              idc_sbci => sg_idc_sbci,     
              idc_sbiw => sg_idc_sbiw,     

              adiw_st  => sg_adiw_st,     
              sbiw_st  => sg_sbiw_st,     

              idc_and  => sg_idc_and,     
              idc_andi => sg_idc_andi,     
              idc_or   => sg_idc_or,     
              idc_ori  => sg_idc_ori,     
              idc_eor  => sg_idc_eor,     
              idc_com  => sg_idc_com,     
              idc_neg  => sg_idc_neg,     

              idc_inc  => sg_idc_inc,     
              idc_dec  => sg_idc_dec,     

              idc_cp   => sg_idc_cp,     
              idc_cpc  => sg_idc_cpc,     
              idc_cpi  => sg_idc_cpi,    
              idc_cpse => sg_idc_cpse,     

              idc_lsr  => sg_idc_lsr,     
              idc_ror  => sg_idc_ror,      
              idc_asr  => sg_idc_asr,      
              idc_swap => sg_idc_swap,      


-- DATA OUTPUT
              alu_data_out => sg_alu_data_out,  

-- FLAGS OUTPUT
              alu_c_flag_out => sg_alu_c_flag_out,
              alu_z_flag_out => sg_alu_z_flag_out,
              alu_n_flag_out => sg_alu_n_flag_out,
              alu_v_flag_out => sg_alu_v_flag_out,
              alu_s_flag_out => sg_alu_s_flag_out,
              alu_h_flag_out => sg_alu_h_flag_out
);



adr      <= sg_adr;     
iowe     <= sg_iowe;
iore     <= sg_iore;
dbusout  <= sg_dbusout;

end struct;