avr_core.vhd

一个FPGA的AVR_Core 仅供测试~

              idc_dec         :in std_logic;

              idc_cp          :in std_logic;              
              idc_cpc         :in std_logic;
              idc_cpi         :in std_logic;
              idc_cpse        :in std_logic;                            

              idc_lsr         :in std_logic;
              idc_ror         :in std_logic;
              idc_asr         :in std_logic;
              idc_swap        :in std_logic;


-- DATA OUTPUT
              alu_data_out    : out std_logic_vector(7 downto 0);

-- FLAGS OUTPUT
              alu_c_flag_out  : out std_logic;
              alu_z_flag_out  : out std_logic;
              alu_n_flag_out  : out std_logic;
              alu_v_flag_out  : out std_logic;
              alu_s_flag_out  : out std_logic;
              alu_h_flag_out  : out std_logic
);

end component;


component reg_file is generic(ResetRegFile : boolean);
	                  port (
          reg_rd_in   : in std_logic_vector  (7 downto 0);
          reg_rd_out  : out std_logic_vector (7 downto 0);
          reg_rd_adr  : in std_logic_vector  (4 downto 0);
          reg_rr_out  : out std_logic_vector (7 downto 0);
          reg_rr_adr  : in std_logic_vector  (4 downto 0);
          reg_rd_wr   : in std_logic;

          post_inc    : in std_logic;                       -- POST INCREMENT FOR LD/ST INSTRUCTIONS
          pre_dec     : in std_logic;                        -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
          reg_h_wr    : in std_logic;
          reg_h_out   : out std_logic_vector (15 downto 0);
          reg_h_adr   : in std_logic_vector (2 downto 0);    -- x,y,z
   		  reg_z_out   : out std_logic_vector (15 downto 0);  -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
		  

          clk         : in std_logic;
          nrst        : in std_logic

 );
end component;

component io_reg_file is port (
          clk         : in std_logic;
          nrst        : in std_logic;

          adr          : in std_logic_vector(5 downto 0);         
          iowe         : in std_logic;         
          dbusout      : in std_logic_vector(7 downto 0);         

          sreg_fl_in   : in std_logic_vector(7 downto 0);         
          sreg_out     : out std_logic_vector(7 downto 0);         

          sreg_fl_wr_en : in  std_logic_vector (7 downto 0);   --FLAGS WRITE ENABLE SIGNALS       

          spl_out      : out std_logic_vector(7 downto 0);         
          sph_out      : out std_logic_vector(7 downto 0);         
          sp_ndown_up  : in std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
          sp_en        : in std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
  
          rampz_out    : out std_logic_vector(7 downto 0)

 );
end component;


component bit_processor is port(
  
              clk             : in std_logic;            
              nrst            : in std_logic;            
              
              bit_num_r_io    : in std_logic_vector (2 downto 0);  -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
              dbusin          : in  std_logic_vector(7 downto 0);  -- SBI/CBI/SBIS/SBIC  IN
              bitpr_io_out    : out std_logic_vector(7 downto 0);  -- SBI/CBI OUT        

              sreg_out        : in  std_logic_vector(7 downto 0);   -- BRBS/BRBC/BLD IN 
              branch     : in  std_logic_vector (2 downto 0);  -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION


              bit_pr_sreg_out : out std_logic_vector(7 downto 0);   -- BCLR/BSET/BST(T-FLAG ONLY)             

              sreg_bit_num    : in std_logic_vector(2 downto 0);    -- BIT NUMBER FOR BCLR/BSET INSTRUCTIONS

              bld_op_out      : out std_logic_vector(7 downto 0);   -- BLD OUT (T FLAG)
              reg_rd_out      : in  std_logic_vector(7 downto 0);   -- BST/SBRS/SBRC IN    

              bit_test_op_out : out std_logic;                      -- OUTPUT OF SBIC/SBIS/SBRS/SBRC


-- OPERATION SIGNALS INPUTS

              -- INSTRUCTUIONS AND STATES

              idc_sbi         : in std_logic;
              sbi_st          : in std_logic;
              idc_cbi         : in std_logic;
              cbi_st          : in std_logic;

              idc_bld         : in std_logic;
              idc_bst         : in std_logic;
              idc_bset        : in std_logic;
              idc_bclr        : in std_logic;

              idc_sbic         : in std_logic;
              idc_sbis         : in std_logic;
              
              idc_sbrs         : in std_logic;
              idc_sbrc         : in std_logic;
              
              idc_brbs         : in std_logic;
              idc_brbc         : in std_logic;

              idc_reti         : in std_logic
                            
);

end component;

component io_adr_dec is port (
          adr          : in std_logic_vector(5 downto 0);         
          iore         : in std_logic;         
          dbusin_ext   : in std_logic_vector(7 downto 0);
          dbusin_int   : out std_logic_vector(7 downto 0);
                    
          spl_out      : in std_logic_vector(7 downto 0); 
          sph_out      : in std_logic_vector(7 downto 0);           
          sreg_out     : in std_logic_vector(7 downto 0);           
          rampz_out    : in std_logic_vector(7 downto 0));
end component;



-- *****************************************************************************************


signal sg_dbusin,sg_dbusout : std_logic_vector (7 downto 0) := (others =>'0');
signal sg_adr             : std_logic_vector (5 downto 0) := (others =>'0');      
signal sg_iowe,sg_iore    :std_logic  := '0';

-- SIGNALS FOR INSTRUCTION AND STATES

signal sg_idc_add,sg_idc_adc,sg_idc_adiw,sg_idc_sub,sg_idc_subi,sg_idc_sbc,sg_idc_sbci,sg_idc_sbiw,
       sg_adiw_st,sg_sbiw_st,sg_idc_and,sg_idc_andi,sg_idc_or,sg_idc_ori,sg_idc_eor,sg_idc_com,
       sg_idc_neg,sg_idc_inc,sg_idc_dec,sg_idc_cp,sg_idc_cpc,sg_idc_cpi,sg_idc_cpse,
       sg_idc_lsr,sg_idc_ror,sg_idc_asr,sg_idc_swap,sg_idc_sbi,sg_sbi_st,sg_idc_cbi,sg_cbi_st,
       sg_idc_bld,sg_idc_bst,sg_idc_bset,sg_idc_bclr,sg_idc_sbic,sg_idc_sbis,sg_idc_sbrs,sg_idc_sbrc,
       sg_idc_brbs,sg_idc_brbc,sg_idc_reti  : std_logic := '0';

signal sg_alu_data_r_in,sg_alu_data_d_in,sg_alu_data_out : std_logic_vector(7 downto 0) := (others =>'0');

signal sg_reg_rd_in,sg_reg_rd_out,sg_reg_rr_out : std_logic_vector  (7 downto 0) := (others =>'0');
signal sg_reg_rd_adr,sg_reg_rr_adr              : std_logic_vector  (4 downto 0) := (others =>'0');
signal sg_reg_h_out,sg_reg_z_out                : std_logic_vector (15 downto 0) := (others =>'0');
signal sg_reg_h_adr                             : std_logic_vector (2 downto 0) := (others =>'0');
signal sg_reg_rd_wr,sg_post_inc,
                       sg_pre_dec,sg_reg_h_wr   : std_logic  := '0';

signal sg_sreg_fl_in,sg_sreg_out,sg_sreg_fl_wr_en,
       sg_spl_out,sg_sph_out,sg_rampz_out                  : std_logic_vector(7 downto 0) := (others =>'0');

signal sg_sp_ndown_up,sg_sp_en : std_logic  := '0';


signal sg_bit_num_r_io,sg_branch,sg_sreg_bit_num  : std_logic_vector (2 downto 0) := (others =>'0');
signal sg_bitpr_io_out,sg_bit_pr_sreg_out,sg_sreg_flags,
       sg_bld_op_out,sg_reg_file_rd_in : std_logic_vector(7 downto 0) := (others =>'0');


signal sg_bit_test_op_out : std_logic  := '0';

signal sg_alu_c_flag_out,sg_alu_z_flag_out,sg_alu_n_flag_out,sg_alu_v_flag_out,
       sg_alu_s_flag_out,sg_alu_h_flag_out  : std_logic  := '0';


begin

main: component pm_fetch_dec port map
(

-- EXTERNAL INTERFACES OF THE CORE
clk      => cp2,
nrst     => ireset,
cpuwait  => cpuwait,

-- PROGRAM MEMORY PORTS
pc       => pc,    
inst     => inst,

-- I/O REGISTERS PORTS
adr      => sg_adr,
iore     => sg_iore,
iowe     => sg_iowe,

-- DATA MEMORY PORTS
ramadr   => ramadr,
ramre    => ramre,
ramwe    => ramwe,

dbusin   => sg_dbusin,
dbusout  => sg_dbusout,

-- INTERRUPTS PORT
irqlines => irqlines,
irqack   => irqack,
irqackad => irqackad,

-- END OF THE CORE INTERFACES


-- *********************************************************************************************
-- ******************** INTERFACES TO THE OTHER BLOCKS *****************************************
-- *********************************************************************************************


-- *********************************************************************************************
-- ******************** INTERFACES TO THE ALU  *************************************************
-- *********************************************************************************************
              alu_data_r_in   => sg_alu_data_r_in,
              alu_data_d_in   => sg_alu_data_d_in,

-- OPERATION SIGNALS INPUTS

              idc_add_out  => sg_idc_add,
              idc_adc_out  => sg_idc_adc,
              idc_adiw_out => sg_idc_adiw,
              idc_sub_out  => sg_idc_sub,
              idc_subi_out => sg_idc_subi,
              idc_sbc_out  => sg_idc_sbc,
              idc_sbci_out => sg_idc_sbci,
              idc_sbiw_out => sg_idc_sbiw,

              adiw_st_out  => sg_adiw_st,
              sbiw_st_out  => sg_sbiw_st,

              idc_and_out  => sg_idc_and,
              idc_andi_out => sg_idc_andi,
              idc_or_out   => sg_idc_or,
              idc_ori_out  => sg_idc_ori,
              idc_eor_out  => sg_idc_eor,
              idc_com_out  => sg_idc_com,
              idc_neg_out  => sg_idc_neg,

              idc_inc_out  => sg_idc_inc,
              idc_dec_out  => sg_idc_dec,

              idc_cp_out   => sg_idc_cp,
              idc_cpc_out  => sg_idc_cpc,
              idc_cpi_out  => sg_idc_cpi,
              idc_cpse_out => sg_idc_cpse,

              idc_lsr_out  => sg_idc_lsr,
              idc_ror_out  => sg_idc_ror,
              idc_asr_out  => sg_idc_asr,
              idc_swap_out => sg_idc_swap,


-- DATA OUTPUT
              alu_data_out => sg_alu_data_out,

-- FLAGS OUTPUT
              alu_c_flag_out => sg_alu_c_flag_out,