spi_s.v

AD7266的Verilog驱动程序,已仿真通过,可直接在EDK下使用.

module spi_s(clk,
              sclk,
              cs_l,
              data_14bit,
              spi_in_bit,
              //data_14bit_temp,
              rst_n
              );
 input clk;
 input rst_n;
 output sclk;
 output cs_l;
 output data_14bit;
 //output data_14bit_temp;
 input  spi_in_bit;
 reg sclk;
 reg [31:0] data_14bit;
 reg [7:0] clk_cnt;
always @ (posedge clk or negedge rst_n)
   begin
    if (!rst_n) 
      clk_cnt <= 12'd0;
    else if (clk_cnt == 12'd50)  //get ?khz SCL clock  
      clk_cnt <= 12'd0;
    else 
      clk_cnt <= clk_cnt + 1'b1;
   end   
  always @ (posedge clk or negedge rst_n)
    begin 
     if (!rst_n)
       sclk <= 1'b0;
     else if (clk_cnt == 12'd50)
       sclk <= ~sclk;       //?khz
    end
 reg [7:0] counter;
 always @(posedge sclk or negedge rst_n)
    begin 
        if(!rst_n)
           counter<=0;
        else if(counter=='d32)
           counter<=0;
        else
           counter<=counter+1'b1;
    end
 reg cs_reg;
 always @(posedge clk or negedge rst_n)
   begin
       if(!rst_n)
         cs_reg<=0;
       else if(counter=='d32)
         cs_reg<=1'b1;
       else
         cs_reg<=0;
   end
  assign cs_l=cs_reg;
 //reg spi_in_reg;
 //reg bit_en;
 reg [31:0] data_14bit_temp;
   always @ (negedge sclk or negedge rst_n)
     begin
         if(!rst_n)
           data_14bit_temp<=0;
         else if(!cs_l)
           data_14bit_temp<={data_14bit_temp,spi_in_bit};
         else 
           data_14bit_temp<=0;
      end
   always @(negedge sclk or negedge rst_n)
     begin
        if(!rst_n)
           data_14bit<=0;
        else if(cs_l)
           data_14bit<=data_14bit_temp>>2;
      end
    
 endmodule