sintab_altera.hier_info

在利用Verilog在FPGA平台上输出正弦波

|Sintab_Altera
sys_clk => sys_clk~0.IN1
sin_output[0] <= sintab:sintab1.port4
sin_output[1] <= sintab:sintab1.port4
sin_output[2] <= sintab:sintab1.port4
sin_output[3] <= sintab:sintab1.port4
sin_output[4] <= sintab:sintab1.port4
sin_output[5] <= sintab:sintab1.port4
sin_output[6] <= sintab:sintab1.port4
sin_output[7] <= sintab:sintab1.port4
sin_output[8] <= sintab:sintab1.port4
sin_output[9] <= sintab:sintab1.port4
sin_output[10] <= sintab:sintab1.port4
sin_output[11] <= sintab:sintab1.port4
sin_output[12] <= sintab:sintab1.port4
sin_output[13] <= sintab:sintab1.port4
counter[0] <= counter[0]~9.DB_MAX_OUTPUT_PORT_TYPE
counter[1] <= counter[1]~8.DB_MAX_OUTPUT_PORT_TYPE
counter[2] <= counter[2]~7.DB_MAX_OUTPUT_PORT_TYPE
counter[3] <= counter[3]~6.DB_MAX_OUTPUT_PORT_TYPE
counter[4] <= counter[4]~5.DB_MAX_OUTPUT_PORT_TYPE
counter[5] <= counter[5]~4.DB_MAX_OUTPUT_PORT_TYPE
counter[6] <= counter[6]~3.DB_MAX_OUTPUT_PORT_TYPE
counter[7] <= counter[7]~2.DB_MAX_OUTPUT_PORT_TYPE
counter[8] <= counter[8]~1.DB_MAX_OUTPUT_PORT_TYPE
counter[9] <= counter[9]~0.DB_MAX_OUTPUT_PORT_TYPE
rst_n => counter[8]~reg0.ACLR
rst_n => counter[7]~reg0.ACLR
rst_n => counter[6]~reg0.ACLR
rst_n => counter[5]~reg0.ACLR
rst_n => counter[4]~reg0.ACLR
rst_n => counter[3]~reg0.ACLR
rst_n => counter[2]~reg0.ACLR
rst_n => counter[1]~reg0.ACLR
rst_n => counter[0]~reg0.ACLR
rst_n => counter[9]~reg0.ACLR


|Sintab_Altera|sintab:sintab1
address[0] => address[0]~9.IN1
address[1] => address[1]~8.IN1
address[2] => address[2]~7.IN1
address[3] => address[3]~6.IN1
address[4] => address[4]~5.IN1
address[5] => address[5]~4.IN1
address[6] => address[6]~3.IN1
address[7] => address[7]~2.IN1
address[8] => address[8]~1.IN1
address[9] => address[9]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~13.IN1
data[1] => data[1]~12.IN1
data[2] => data[2]~11.IN1
data[3] => data[3]~10.IN1
data[4] => data[4]~9.IN1
data[5] => data[5]~8.IN1
data[6] => data[6]~7.IN1
data[7] => data[7]~6.IN1
data[8] => data[8]~5.IN1
data[9] => data[9]~4.IN1
data[10] => data[10]~3.IN1
data[11] => data[11]~2.IN1
data[12] => data[12]~1.IN1
data[13] => data[13]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a


|Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component
wren_a => altsyncram_a851:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_a851:auto_generated.data_a[0]
data_a[1] => altsyncram_a851:auto_generated.data_a[1]
data_a[2] => altsyncram_a851:auto_generated.data_a[2]
data_a[3] => altsyncram_a851:auto_generated.data_a[3]
data_a[4] => altsyncram_a851:auto_generated.data_a[4]
data_a[5] => altsyncram_a851:auto_generated.data_a[5]
data_a[6] => altsyncram_a851:auto_generated.data_a[6]
data_a[7] => altsyncram_a851:auto_generated.data_a[7]
data_a[8] => altsyncram_a851:auto_generated.data_a[8]
data_a[9] => altsyncram_a851:auto_generated.data_a[9]
data_a[10] => altsyncram_a851:auto_generated.data_a[10]
data_a[11] => altsyncram_a851:auto_generated.data_a[11]
data_a[12] => altsyncram_a851:auto_generated.data_a[12]
data_a[13] => altsyncram_a851:auto_generated.data_a[13]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_a851:auto_generated.address_a[0]
address_a[1] => altsyncram_a851:auto_generated.address_a[1]
address_a[2] => altsyncram_a851:auto_generated.address_a[2]
address_a[3] => altsyncram_a851:auto_generated.address_a[3]
address_a[4] => altsyncram_a851:auto_generated.address_a[4]
address_a[5] => altsyncram_a851:auto_generated.address_a[5]
address_a[6] => altsyncram_a851:auto_generated.address_a[6]
address_a[7] => altsyncram_a851:auto_generated.address_a[7]
address_a[8] => altsyncram_a851:auto_generated.address_a[8]
address_a[9] => altsyncram_a851:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_a851:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_a851:auto_generated.q_a[0]
q_a[1] <= altsyncram_a851:auto_generated.q_a[1]
q_a[2] <= altsyncram_a851:auto_generated.q_a[2]
q_a[3] <= altsyncram_a851:auto_generated.q_a[3]
q_a[4] <= altsyncram_a851:auto_generated.q_a[4]
q_a[5] <= altsyncram_a851:auto_generated.q_a[5]
q_a[6] <= altsyncram_a851:auto_generated.q_a[6]
q_a[7] <= altsyncram_a851:auto_generated.q_a[7]
q_a[8] <= altsyncram_a851:auto_generated.q_a[8]
q_a[9] <= altsyncram_a851:auto_generated.q_a[9]
q_a[10] <= altsyncram_a851:auto_generated.q_a[10]
q_a[11] <= altsyncram_a851:auto_generated.q_a[11]
q_a[12] <= altsyncram_a851:auto_generated.q_a[12]
q_a[13] <= altsyncram_a851:auto_generated.q_a[13]
q_b[0] <= <GND>


|Sintab_Altera|sintab:sintab1|altsyncram:altsyncram_component|altsyncram_a851:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE