sintab_altera.map.eqn

在利用Verilog在FPGA平台上输出正弦波

D1_q_a[13]_PORT_A_data_out = MEMORY(D1_q_a[13]_PORT_A_data_in_reg, , D1_q_a[13]_PORT_A_address_reg, D1_q_a[13]_PORT_B_address_reg, D1_q_a[13]_PORT_A_write_enable_reg, , , , D1_q_a[13]_clock_0, , , , , );
D1_q_a[13]_PORT_A_data_out_reg = DFFE(D1_q_a[13]_PORT_A_data_out, D1_q_a[13]_clock_0, , , );
D1_q_a[13] = D1_q_a[13]_PORT_A_data_out_reg[0];


--A1L5Q is counter[0]~reg0
A1L5Q = DFFEAS(A1L3, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L9Q is counter[1]~reg0
A1L9Q = DFFEAS(A1L7, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L13Q is counter[2]~reg0
A1L13Q = DFFEAS(A1L11, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L17Q is counter[3]~reg0
A1L17Q = DFFEAS(A1L15, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L21Q is counter[4]~reg0
A1L21Q = DFFEAS(A1L19, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L25Q is counter[5]~reg0
A1L25Q = DFFEAS(A1L23, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L29Q is counter[6]~reg0
A1L29Q = DFFEAS(A1L27, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L33Q is counter[7]~reg0
A1L33Q = DFFEAS(A1L31, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L37Q is counter[8]~reg0
A1L37Q = DFFEAS(A1L35, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L41Q is counter[9]~reg0
A1L41Q = DFFEAS(A1L39, sys_clk, rst_n,  ,  ,  ,  ,  ,  );


--A1L3 is counter[0]~90
A1L3 = A1L5Q $ VCC;

--A1L4 is counter[0]~91
A1L4 = CARRY(A1L5Q);


--A1L7 is counter[1]~92
A1L7 = A1L9Q & !A1L4 # !A1L9Q & (A1L4 # GND);

--A1L8 is counter[1]~93
A1L8 = CARRY(!A1L4 # !A1L9Q);


--A1L11 is counter[2]~94
A1L11 = A1L13Q & (A1L8 $ GND) # !A1L13Q & !A1L8 & VCC;

--A1L12 is counter[2]~95
A1L12 = CARRY(A1L13Q & !A1L8);


--A1L15 is counter[3]~96
A1L15 = A1L17Q & !A1L12 # !A1L17Q & (A1L12 # GND);

--A1L16 is counter[3]~97
A1L16 = CARRY(!A1L12 # !A1L17Q);


--A1L19 is counter[4]~98
A1L19 = A1L21Q & (A1L16 $ GND) # !A1L21Q & !A1L16 & VCC;

--A1L20 is counter[4]~99
A1L20 = CARRY(A1L21Q & !A1L16);


--A1L23 is counter[5]~100
A1L23 = A1L25Q & !A1L20 # !A1L25Q & (A1L20 # GND);

--A1L24 is counter[5]~101
A1L24 = CARRY(!A1L20 # !A1L25Q);


--A1L27 is counter[6]~102
A1L27 = A1L29Q & (A1L24 $ GND) # !A1L29Q & !A1L24 & VCC;

--A1L28 is counter[6]~103
A1L28 = CARRY(A1L29Q & !A1L24);


--A1L31 is counter[7]~104
A1L31 = A1L33Q & !A1L28 # !A1L33Q & (A1L28 # GND);

--A1L32 is counter[7]~105
A1L32 = CARRY(!A1L28 # !A1L33Q);


--A1L35 is counter[8]~106
A1L35 = A1L37Q & (A1L32 $ GND) # !A1L37Q & !A1L32 & VCC;

--A1L36 is counter[8]~107
A1L36 = CARRY(A1L37Q & !A1L32);


--A1L39 is counter[9]~108
A1L39 = A1L41Q $ A1L36;


--~GND is ~GND
~GND = GND;


--sys_clk is sys_clk
--operation mode is input

sys_clk = INPUT();


--rst_n is rst_n
--operation mode is input

rst_n = INPUT();


--sin_output[0] is sin_output[0]
--operation mode is output

sin_output[0] = OUTPUT(D1_q_a[0]);


--sin_output[1] is sin_output[1]
--operation mode is output

sin_output[1] = OUTPUT(D1_q_a[1]);


--sin_output[2] is sin_output[2]
--operation mode is output

sin_output[2] = OUTPUT(D1_q_a[2]);


--sin_output[3] is sin_output[3]
--operation mode is output

sin_output[3] = OUTPUT(D1_q_a[3]);


--sin_output[4] is sin_output[4]
--operation mode is output

sin_output[4] = OUTPUT(D1_q_a[4]);


--sin_output[5] is sin_output[5]
--operation mode is output

sin_output[5] = OUTPUT(D1_q_a[5]);


--sin_output[6] is sin_output[6]
--operation mode is output

sin_output[6] = OUTPUT(D1_q_a[6]);


--sin_output[7] is sin_output[7]
--operation mode is output

sin_output[7] = OUTPUT(D1_q_a[7]);


--sin_output[8] is sin_output[8]
--operation mode is output

sin_output[8] = OUTPUT(D1_q_a[8]);


--sin_output[9] is sin_output[9]
--operation mode is output

sin_output[9] = OUTPUT(D1_q_a[9]);


--sin_output[10] is sin_output[10]
--operation mode is output

sin_output[10] = OUTPUT(D1_q_a[10]);


--sin_output[11] is sin_output[11]
--operation mode is output

sin_output[11] = OUTPUT(D1_q_a[11]);


--sin_output[12] is sin_output[12]
--operation mode is output

sin_output[12] = OUTPUT(D1_q_a[12]);


--sin_output[13] is sin_output[13]
--operation mode is output

sin_output[13] = OUTPUT(D1_q_a[13]);


--counter[0] is counter[0]
--operation mode is output

counter[0] = OUTPUT(A1L5Q);


--counter[1] is counter[1]
--operation mode is output

counter[1] = OUTPUT(A1L9Q);


--counter[2] is counter[2]
--operation mode is output

counter[2] = OUTPUT(A1L13Q);


--counter[3] is counter[3]
--operation mode is output

counter[3] = OUTPUT(A1L17Q);


--counter[4] is counter[4]
--operation mode is output

counter[4] = OUTPUT(A1L21Q);


--counter[5] is counter[5]
--operation mode is output

counter[5] = OUTPUT(A1L25Q);


--counter[6] is counter[6]
--operation mode is output

counter[6] = OUTPUT(A1L29Q);


--counter[7] is counter[7]
--operation mode is output

counter[7] = OUTPUT(A1L33Q);


--counter[8] is counter[8]
--operation mode is output

counter[8] = OUTPUT(A1L37Q);


--counter[9] is counter[9]
--operation mode is output

counter[9] = OUTPUT(A1L41Q);