📄 static_display.vhd
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library ieee;--数码管静态显示实验
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity static_display is
port( clk:in std_logic;--系统时钟信号,40MHz
key: in std_logic;
q1,q2:out std_logic_vector(7 downto 0)--两个静态数码管的输入信号
);
end entity;
architecture miao of static_display is
signal n1:integer range 0 to 19999;--分频系数
signal n2:integer range 0 to 499;--分频系数
signal n3:integer range 0 to 19;
signal a1,a2:std_logic_vector(3 downto 0);
signal cp1,cp2:std_logic;
begin
process(clk)--分频得到1KHz
begin
if clk'event and clk='1' then
if n1<19999 then
n1<=n1+1;
else
n1<=0;cp1<=not cp1;
end if;
end if;
end process;
process(cp1)--消抖电路
begin
if key='1' then
n3<=0;
elsif cp1'event and cp1='1' then
if n3<19 then
n3<=n3+1;
else
n3<=19;
end if;
end if;
end process;
process(cp1)--分频得到1Hz
begin
if cp1'event and cp1='1' then
if n2<499 then
n2<=n2+1;
else
n2<=0;cp2<=not cp2;
end if;
end if;
end process;
process(cp2)--数据显示,这里采用静态显示方式
begin
if n3=19 then
a1<="0000";
a2<="0000";
elsif cp2'event and cp2='1' then
if a1<"1001" then
a1<=a1+"0001";
elsif a2<"1001" then
a1<="0000";
a2<=a2+"0001";
else
a1<="0000";
a2<="0000";
end if;
end if;
end process;
process
begin
case a1 is
when "0000"=>q1<="00111111";--h-a
when "0001"=>q1<="00000110";
when "0010"=>q1<="01011011";
when "0011"=>q1<="01001111";
when "0100" =>q1<="01100110";
when "0101"=>q1<="01101101";
when "0110"=>q1<="01111101";
when "0111"=>q1<="00000111";
when "1000"=>q1<="01111111";
when "1001"=>q1<="01101111";
when others=>q1<="00000000";
end case;
case a2 is
when "0000"=>q2<="00111111";--h-a
when "0001"=>q2<="00000110";
when "0010"=>q2<="01011011";
when "0011"=>q2<="01001111";
when "0100" =>q2<="01100110";
when "0101"=>q2<="01101101";
when "0110"=>q2<="01111101";
when "0111"=>q2<="00000111";
when "1000"=>q2<="01111111";
when "1001"=>q2<="01101111";
when others=>q2<="00000000";
end case;
end process;
end miao ;
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