📄 static_display.rpt
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_LC2_C3~NOT = LCELL( _EQ064);
_EQ064 = a11 & a13
# a12 & a13
# a10 & a13;
-- Node name is ':1174'
-- Equation name is '_LC4_A8', type is buried
_LC4_A8 = LCELL( _EQ065);
_EQ065 = !a23
# _LC8_A8;
-- Node name is ':1176'
-- Equation name is '_LC8_A8', type is buried
_LC8_A8 = LCELL( _EQ066);
_EQ066 = !a20 & !a21 & !a22;
-- Node name is ':1803'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = LCELL( _EQ067);
_EQ067 = !a10 & !a11 & a12 & !a13;
-- Node name is ':1827'
-- Equation name is '_LC4_C1', type is buried
!_LC4_C1 = _LC4_C1~NOT;
_LC4_C1~NOT = LCELL( _EQ068);
_EQ068 = a13
# a10
# !a11
# a12;
-- Node name is ':1839'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = LCELL( _EQ069);
_EQ069 = a10 & !a11 & !a12 & !a13;
-- Node name is ':1851'
-- Equation name is '_LC3_C3', type is buried
_LC3_C3 = LCELL( _EQ070);
_EQ070 = !a10 & !a11 & !a12 & !a13;
-- Node name is '~1889~1'
-- Equation name is '~1889~1', location is LC3_C4, type is buried.
-- synthesized logic cell
!_LC3_C4 = _LC3_C4~NOT;
_LC3_C4~NOT = LCELL( _EQ071);
_EQ071 = _LC4_C3
# _LC3_C3;
-- Node name is ':1889'
-- Equation name is '_LC2_C4', type is buried
_LC2_C4 = LCELL( _EQ072);
_EQ072 = _LC3_C4 & _LC8_C4
# _LC3_C4 & _LC7_C4
# _LC3_C4 & _LC4_C4;
-- Node name is ':1920'
-- Equation name is '_LC1_C4', type is buried
_LC1_C4 = LCELL( _EQ073);
_EQ073 = _LC5_C4 & _LC8_C4
# _LC5_C4 & _LC7_C4
# _LC3_C3;
-- Node name is '~1922~1'
-- Equation name is '~1922~1', location is LC5_C4, type is buried.
-- synthesized logic cell
!_LC5_C4 = _LC5_C4~NOT;
_LC5_C4~NOT = LCELL( _EQ074);
_EQ074 = _LC4_C4
# _LC4_C3;
-- Node name is '~1949~1'
-- Equation name is '~1949~1', location is LC3_C1, type is buried.
-- synthesized logic cell
!_LC3_C1 = _LC3_C1~NOT;
_LC3_C1~NOT = LCELL( _EQ075);
_EQ075 = !a10 & !a11 & a12 & !a13
# a10 & a11 & !a12 & !a13;
-- Node name is ':1949'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = LCELL( _EQ076);
_EQ076 = !a10 & !a11 & !a12 & a13
# !a10 & a11 & a12 & !a13;
-- Node name is ':1953'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = LCELL( _EQ077);
_EQ077 = !_LC4_C3 & _LC7_C3
# _LC4_C1 & !_LC4_C3
# _LC3_C3;
-- Node name is ':1971'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = LCELL( _EQ078);
_EQ078 = !a11 & !a12 & a13
# a10 & !a11 & a12 & !a13
# !a10 & a11 & a12 & !a13;
-- Node name is ':1986'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ079);
_EQ079 = !a10 & !a12 & !a13
# a11 & !a12 & !a13
# !a11 & !a12 & a13
# !a10 & !a11 & !a12
# a10 & !a11 & a12 & !a13
# !a10 & a11 & !a13;
-- Node name is ':2019'
-- Equation name is '_LC7_C1', type is buried
_LC7_C1 = LCELL( _EQ080);
_EQ080 = !_LC3_C4
# !_LC3_C1 & !_LC4_C1
# _LC1_C3 & !_LC4_C1;
-- Node name is ':2042'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = LCELL( _EQ081);
_EQ081 = !a11 & !a12 & a13
# a10 & a11 & a12 & !a13;
-- Node name is ':2052'
-- Equation name is '_LC6_C4', type is buried
_LC6_C4 = LCELL( _EQ082);
_EQ082 = !_LC5_C4
# _LC3_C3
# _LC7_C4
# _LC6_C3;
-- Node name is ':2070'
-- Equation name is '_LC1_C3', type is buried
_LC1_C3 = LCELL( _EQ083);
_EQ083 = a10 & a12 & !a13
# !a11 & !a12 & a13
# a11 & a12 & !a13;
-- Node name is '~2079~1'
-- Equation name is '~2079~1', location is LC4_C4, type is buried.
-- synthesized logic cell
_LC4_C4 = LCELL( _EQ084);
_EQ084 = a11 & !a12 & !a13;
-- Node name is ':2085'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ085);
_EQ085 = !a10 & !a12 & !a13
# a10 & a12 & !a13
# !a11 & !a12 & a13
# !a10 & !a11 & !a12
# a11 & !a13;
-- Node name is ':2373'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ086);
_EQ086 = a20 & !a21 & !a22 & !a23;
-- Node name is ':2415'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ087);
_EQ087 = !a21 & !a22 & a23
# !a20 & a22 & !a23
# !a21 & a22 & !a23
# !a20 & a21 & !a23
# a21 & !a22 & !a23;
-- Node name is ':2423'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ088);
_EQ088 = a23 & !_LC2_A6 & _LC5_A6
# !_LC2_A6 & _LC5_A6 & !_LC8_A8;
-- Node name is ':2454'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ089);
_EQ089 = !a21 & a22 & !a23
# !a20 & a22 & !a23
# !a20 & !a21 & !a23
# !a21 & !a22 & a23
# !a20 & !a21 & !a22;
-- Node name is ':2487'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ090);
_EQ090 = !a20 & !a22 & !a23
# !a20 & !a21 & !a22
# !a20 & a21 & !a23;
-- Node name is ':2520'
-- Equation name is '_LC4_A7', type is buried
_LC4_A7 = LCELL( _EQ091);
_EQ091 = !a20 & !a22 & !a23
# a21 & !a22 & !a23
# !a21 & !a22 & a23
# !a20 & !a21 & !a22
# a20 & !a21 & a22 & !a23
# !a20 & a21 & !a23;
-- Node name is ':2553'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ092);
_EQ092 = !a21 & !a23
# a20 & !a23
# !a21 & !a22
# a22 & !a23;
-- Node name is '~2586~1'
-- Equation name is '~2586~1', location is LC3_A6, type is buried.
-- synthesized logic cell
_LC3_A6 = LCELL( _EQ093);
_EQ093 = !a20 & !a21 & !a23
# !a21 & !a22 & a23
# !a20 & !a21 & !a22
# a20 & a21 & a22 & !a23;
-- Node name is ':2586'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ094);
_EQ094 = _LC2_A6
# _LC1_A6
# _LC3_A6;
-- Node name is '~2613~1'
-- Equation name is '~2613~1', location is LC1_A6, type is buried.
-- synthesized logic cell
_LC1_A6 = LCELL( _EQ095);
_EQ095 = a21 & !a22 & !a23;
-- Node name is ':2619'
-- Equation name is '_LC2_A11', type is buried
_LC2_A11 = LCELL( _EQ096);
_EQ096 = !a20 & !a22 & !a23
# a20 & a22 & !a23
# !a21 & !a22 & a23
# !a20 & !a21 & !a22
# a21 & !a23;
Project Information c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,836K
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