📄 static_display.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 05 OR2 ! 0 2 0 3 |LPM_ADD_SUB:252|addcore:adder|:103
- 5 - C 05 OR2 ! 0 3 0 3 |LPM_ADD_SUB:252|addcore:adder|:111
- 2 - C 12 AND2 0 4 0 4 |LPM_ADD_SUB:252|addcore:adder|:123
- 4 - C 07 AND2 0 3 0 1 |LPM_ADD_SUB:252|addcore:adder|:131
- 8 - C 07 AND2 0 4 0 4 |LPM_ADD_SUB:252|addcore:adder|:135
- 4 - C 10 AND2 0 3 0 1 |LPM_ADD_SUB:252|addcore:adder|:143
- 1 - C 10 AND2 0 4 0 2 |LPM_ADD_SUB:252|addcore:adder|:147
- 2 - C 06 AND2 0 2 0 5 |LPM_ADD_SUB:667|addcore:adder|:63
- 3 - C 12 AND2 0 3 0 4 |LPM_ADD_SUB:865|addcore:adder|:83
- 3 - C 02 AND2 0 2 0 1 |LPM_ADD_SUB:865|addcore:adder|:87
- 3 - C 09 AND2 0 4 0 3 |LPM_ADD_SUB:865|addcore:adder|:95
- 6 - C 09 AND2 0 2 0 1 |LPM_ADD_SUB:865|addcore:adder|:99
- 6 - A 08 AND2 0 2 0 1 |LPM_ADD_SUB:1228|addcore:adder|:55
- 7 - A 08 AND2 0 3 0 1 |LPM_ADD_SUB:1228|addcore:adder|:59
- 3 - C 10 DFFE + 0 3 0 1 n114 (:19)
- 8 - C 10 DFFE + 0 2 0 2 n113 (:20)
- 6 - C 10 DFFE + 0 2 0 2 n112 (:21)
- 2 - C 10 DFFE + 0 3 0 3 n111 (:22)
- 5 - C 10 DFFE + 0 2 0 4 n110 (:23)
- 5 - C 07 DFFE + 0 2 0 2 n19 (:24)
- 7 - C 07 DFFE + 0 3 0 3 n18 (:25)
- 6 - C 07 DFFE + 0 2 0 4 n17 (:26)
- 5 - C 12 DFFE + 0 3 0 2 n16 (:27)
- 1 - C 12 DFFE + 0 2 0 3 n15 (:28)
- 2 - C 05 DFFE + 0 2 0 2 n14 (:29)
- 6 - C 05 DFFE + 0 3 0 1 n13 (:30)
- 7 - C 05 DFFE + 0 2 0 2 n12 (:31)
- 4 - C 05 DFFE + 0 2 0 1 n11 (:32)
- 3 - C 05 DFFE + 0 1 0 2 n10 (:33)
- 7 - C 12 DFFE + 0 1 0 15 cp1 (:34)
- 8 - C 06 DFFE 1 4 0 5 n34 (:35)
- 6 - C 06 DFFE 1 4 0 3 n33 (:36)
- 7 - C 06 DFFE 1 4 0 4 n32 (:37)
- 4 - C 06 DFFE 1 4 0 1 n31 (:38)
- 5 - C 06 DFFE 1 3 0 2 n30 (:39)
- 7 - C 09 DFFE 0 4 0 1 n28 (:40)
- 5 - C 09 DFFE 0 4 0 2 n27 (:41)
- 4 - C 09 DFFE 0 3 0 3 n26 (:42)
- 8 - C 09 DFFE 0 4 0 2 n25 (:43)
- 2 - C 02 DFFE 0 4 0 3 n24 (:44)
- 6 - C 02 DFFE 0 3 0 4 n23 (:45)
- 8 - C 12 DFFE 0 4 0 2 n22 (:46)
- 8 - C 02 DFFE 0 3 0 3 n21 (:47)
- 4 - C 12 DFFE 0 2 0 4 n20 (:48)
- 7 - C 02 DFFE 0 2 0 8 cp2 (:49)
- 5 - C 03 DFFE 0 5 0 13 a13 (:50)
- 5 - C 02 DFFE 0 5 0 14 a12 (:51)
- 1 - C 02 DFFE 0 4 0 15 a11 (:52)
- 4 - C 02 DFFE 0 3 0 15 a10 (:53)
- 1 - A 08 DFFE 0 5 0 11 a23 (:54)
- 3 - A 08 DFFE 0 5 0 11 a22 (:55)
- 2 - A 08 DFFE 0 5 0 12 a21 (:56)
- 5 - A 08 DFFE 0 4 0 12 a20 (:57)
- 7 - C 10 OR2 0 4 0 16 :119
- 3 - C 07 OR2 s 0 3 0 1 ~134~1
- 2 - C 07 OR2 0 4 0 1 :134
- 1 - C 07 AND2 s 0 3 0 1 ~146~1
- 8 - C 05 OR2 0 2 0 3 :169
- 3 - C 06 AND2 0 3 0 3 :626
- 2 - C 09 OR2 s 0 3 0 1 ~786~1
- 1 - C 09 OR2 0 4 0 10 :786
- 6 - C 12 OR2 0 4 0 1 :808
- 1 - C 06 OR2 ! 0 4 0 8 :1117
- 2 - C 03 OR2 ! 0 4 0 7 :1153
- 4 - A 08 OR2 0 2 0 3 :1174
- 8 - A 08 AND2 0 3 0 3 :1176
- 7 - C 04 AND2 0 4 0 3 :1803
- 4 - C 01 OR2 ! 0 4 0 2 :1827
- 4 - C 03 AND2 0 4 0 3 :1839
- 3 - C 03 AND2 0 4 0 4 :1851
- 3 - C 04 OR2 s ! 0 2 0 2 ~1889~1
- 2 - C 04 OR2 0 4 1 0 :1889
- 1 - C 04 OR2 0 4 1 0 :1920
- 5 - C 04 OR2 s ! 0 2 0 2 ~1922~1
- 3 - C 01 OR2 s ! 0 4 0 1 ~1949~1
- 7 - C 03 OR2 0 4 0 1 :1949
- 1 - C 01 OR2 0 4 1 0 :1953
- 8 - C 04 OR2 0 4 0 2 :1971
- 2 - C 01 OR2 0 4 1 0 :1986
- 7 - C 01 OR2 0 4 1 0 :2019
- 6 - C 03 OR2 0 4 0 1 :2042
- 6 - C 04 OR2 0 4 1 0 :2052
- 1 - C 03 OR2 0 4 0 1 :2070
- 4 - C 04 AND2 s 0 3 0 2 ~2079~1
- 8 - C 03 OR2 0 4 1 0 :2085
- 2 - A 06 AND2 0 4 0 2 :2373
- 5 - A 06 OR2 0 4 0 1 :2415
- 6 - A 06 OR2 0 4 1 0 :2423
- 4 - A 06 OR2 0 4 1 0 :2454
- 1 - A 07 OR2 0 4 1 0 :2487
- 4 - A 07 OR2 0 4 1 0 :2520
- 4 - A 10 OR2 0 4 1 0 :2553
- 3 - A 06 OR2 s 0 4 0 1 ~2586~1
- 2 - A 09 OR2 0 3 1 0 :2586
- 1 - A 06 AND2 s 0 3 0 1 ~2613~1
- 2 - A 11 OR2 0 4 1 0 :2619
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 12/ 48( 25%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/ 96( 8%) 28/ 48( 58%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
DFF 16 cp1
DFF 9 cp2
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 8 :1117
INPUT 5 key
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** EQUATIONS **
clk : INPUT;
key : INPUT;
-- Node name is ':53' = 'a10'
-- Equation name is 'a10', location is LC4_C2, type is buried.
a10 = DFFE( _EQ001, cp2, !_LC1_C6, VCC, VCC);
_EQ001 = !a10 & _LC2_C3;
-- Node name is ':52' = 'a11'
-- Equation name is 'a11', location is LC1_C2, type is buried.
a11 = DFFE( _EQ002, cp2, !_LC1_C6, VCC, VCC);
_EQ002 = !a10 & a11 & _LC2_C3
# a10 & !a11 & _LC2_C3;
-- Node name is ':51' = 'a12'
-- Equation name is 'a12', location is LC5_C2, type is buried.
a12 = DFFE( _EQ003, cp2, !_LC1_C6, VCC, VCC);
_EQ003 = !a11 & a12 & _LC2_C3
# !a10 & a12 & _LC2_C3
# a10 & a11 & !a12 & _LC2_C3;
-- Node name is ':50' = 'a13'
-- Equation name is 'a13', location is LC5_C3, type is buried.
a13 = DFFE( _EQ004, cp2, !_LC1_C6, VCC, VCC);
_EQ004 = a10 & a11 & a12 & !a13
# !a10 & !a11 & !a12 & a13;
-- Node name is ':57' = 'a20'
-- Equation name is 'a20', location is LC5_A8, type is buried.
a20 = DFFE( _EQ005, cp2, !_LC1_C6, VCC, VCC);
_EQ005 = a20 & _LC2_C3
# !a20 & !_LC2_C3 & _LC4_A8;
-- Node name is ':56' = 'a21'
-- Equation name is 'a21', location is LC2_A8, type is buried.
a21 = DFFE( _EQ006, cp2, !_LC1_C6, VCC, VCC);
_EQ006 = a21 & _LC2_C3
# !a20 & a21 & _LC4_A8
# a20 & !a21 & !_LC2_C3 & _LC4_A8;
-- Node name is ':55' = 'a22'
-- Equation name is 'a22', location is LC3_A8, type is buried.
a22 = DFFE( _EQ007, cp2, !_LC1_C6, VCC, VCC);
_EQ007 = a22 & _LC2_C3
# a22 & _LC4_A8 & !_LC6_A8
# !a22 & !_LC2_C3 & _LC4_A8 & _LC6_A8;
-- Node name is ':54' = 'a23'
-- Equation name is 'a23', location is LC1_A8, type is buried.
a23 = DFFE( _EQ008, cp2, !_LC1_C6, VCC, VCC);
_EQ008 = a23 & _LC2_C3
# a23 & !_LC7_A8 & _LC8_A8
# !a23 & !_LC2_C3 & _LC7_A8;
-- Node name is ':34' = 'cp1'
-- Equation name is 'cp1', location is LC7_C12, type is buried.
cp1 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !cp1 & !_LC7_C10
# cp1 & _LC7_C10;
-- Node name is ':49' = 'cp2'
-- Equation name is 'cp2', location is LC7_C2, type is buried.
cp2 = DFFE( _EQ010, cp1, VCC, VCC, VCC);
_EQ010 = !cp2 & !_LC1_C9
# cp2 & _LC1_C9;
-- Node name is ':33' = 'n10'
-- Equation name is 'n10', location is LC3_C5, type is buried.
n10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = _LC7_C10 & !n10;
-- Node name is ':32' = 'n11'
-- Equation name is 'n11', location is LC4_C5, type is buried.
n11 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC7_C10 & n10 & !n11
# _LC7_C10 & !n10 & n11;
-- Node name is ':31' = 'n12'
-- Equation name is 'n12', location is LC7_C5, type is buried.
n12 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !_LC1_C5 & _LC7_C10 & n12
# _LC1_C5 & _LC7_C10 & !n12;
-- Node name is ':30' = 'n13'
-- Equation name is 'n13', location is LC6_C5, type is buried.
n13 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = _LC7_C10 & !n12 & n13
# !_LC1_C5 & _LC7_C10 & n13
# _LC1_C5 & _LC7_C10 & n12 & !n13;
-- Node name is ':29' = 'n14'
-- Equation name is 'n14', location is LC2_C5, type is buried.
n14 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !_LC5_C5 & _LC7_C10 & n14
# _LC5_C5 & _LC7_C10 & !n14;
-- Node name is ':28' = 'n15'
-- Equation name is 'n15', location is LC1_C12, type is buried.
n15 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = _LC7_C10 & _LC8_C5 & n15
# _LC7_C10 & !_LC8_C5 & !n15;
-- Node name is ':27' = 'n16'
-- Equation name is 'n16', location is LC5_C12, type is buried.
n16 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC7_C10 & !n15 & n16
# _LC7_C10 & _LC8_C5 & n16
# _LC7_C10 & !_LC8_C5 & n15 & !n16;
-- Node name is ':26' = 'n17'
-- Equation name is 'n17', location is LC6_C7, type is buried.
n17 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = !_LC2_C12 & _LC7_C10 & n17
# _LC2_C12 & _LC7_C10 & !n17;
-- Node name is ':25' = 'n18'
-- Equation name is 'n18', location is LC7_C7, type is buried.
n18 = DFFE( _EQ019, GLOBAL( clk), VCC, VCC, VCC);
_EQ019 = _LC7_C10 & !n17 & n18
# !_LC2_C12 & _LC7_C10 & n18
# _LC2_C12 & _LC7_C10 & n17 & !n18;
-- Node name is ':24' = 'n19'
-- Equation name is 'n19', location is LC5_C7, type is buried.
n19 = DFFE( _EQ020, GLOBAL( clk), VCC, VCC, VCC);
_EQ020 = !_LC4_C7 & _LC7_C10 & n19
# _LC4_C7 & _LC7_C10 & !n19;
-- Node name is ':48' = 'n20'
-- Equation name is 'n20', location is LC4_C12, type is buried.
n20 = DFFE( _EQ021, cp1, VCC, VCC, VCC);
_EQ021 = _LC1_C9 & !n20;
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