📄 static_display.rpt
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Project Information c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/18/2007 11:14:46
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
STATIC_DISPLAY
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
static_display
EPF10K10TC144-4 2 16 0 0 0 % 96 16 %
User Pins: 2 16 0
Project Information c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
static_display@125 clk
static_display@28 key
static_display@113 q10
static_display@112 q11
static_display@111 q12
static_display@110 q13
static_display@109 q14
static_display@102 q15
static_display@101 q16
static_display@100 q17
static_display@122 q20
static_display@121 q21
static_display@120 q22
static_display@119 q23
static_display@118 q24
static_display@117 q25
static_display@116 q26
static_display@114 q27
Project Information c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
** FILE HIERARCHY **
|lpm_add_sub:252|
|lpm_add_sub:252|addcore:adder|
|lpm_add_sub:252|altshift:result_ext_latency_ffs|
|lpm_add_sub:252|altshift:carry_ext_latency_ffs|
|lpm_add_sub:252|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:667|
|lpm_add_sub:667|addcore:adder|
|lpm_add_sub:667|altshift:result_ext_latency_ffs|
|lpm_add_sub:667|altshift:carry_ext_latency_ffs|
|lpm_add_sub:667|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:865|
|lpm_add_sub:865|addcore:adder|
|lpm_add_sub:865|altshift:result_ext_latency_ffs|
|lpm_add_sub:865|altshift:carry_ext_latency_ffs|
|lpm_add_sub:865|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1203|
|lpm_add_sub:1203|addcore:adder|
|lpm_add_sub:1203|altshift:result_ext_latency_ffs|
|lpm_add_sub:1203|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1203|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1228|
|lpm_add_sub:1228|addcore:adder|
|lpm_add_sub:1228|altshift:result_ext_latency_ffs|
|lpm_add_sub:1228|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1228|altshift:oflow_ext_latency_ffs|
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
***** Logic for device 'static_display' compiled without errors.
Device: EPF10K10TC144-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R
E E E E E E E E E E E E E E
S S S S S S S S S S S S S S G G G V
E E E E E G E E E E V E E E E G E N N N C V
R R R R R N R R R R C R R R R N R D D D C C
V V V V V D V V V V C V V V V D V I I c I I q q q q q q q C q q q q q q
E E E E E I E E E E I E E E E I E N N l N N 2 2 2 2 2 2 2 I 2 1 1 1 1 1
D D D D D O D D D D O D D D D O D T T k T T 0 1 2 3 4 5 6 O 7 0 1 2 3 4
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | q15
RESERVED | 8 101 | q16
RESERVED | 9 100 | q17
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K10TC144-4 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
key | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R G R V V G G G G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E N E C C N N N N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S D S C C D D D D D S S C S S S S D S S S S C S
E E E I E E E E I E E E E I E I I I I I I I E E I E E E E I E E E E I E
R R R O R R R R O R R R R O R N N N N N N N R R O R R R R O R R R R O R
V V V V V V V V V V V V T T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A6 6/ 8( 75%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
A7 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
A9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
C1 5/ 8( 62%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 9/22( 40%)
C2 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 2/2 1/2 6/22( 27%)
C3 8/ 8(100%) 2/ 8( 25%) 7/ 8( 87%) 1/2 1/2 5/22( 22%)
C4 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
C5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
C6 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/22( 9%)
C7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 7/22( 31%)
C9 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 6/22( 27%)
C10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
C12 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 2/2 0/2 7/22( 31%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 17/96 ( 17%)
Total logic cells used: 96/576 ( 16%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.41/4 ( 85%)
Total fan-in: 328/2304 ( 14%)
Total input pins required: 2
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 96
Total flipflops required: 39
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 9/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 6 2 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 5 8 8 8 8 8 8 0 8 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 77/0
Total: 5 8 8 8 8 14 10 8 9 9 1 8 0 0 0 0 0 0 0 0 0 0 0 0 0 96/0
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G 0 0 0 0 clk
28 - - C -- INPUT 0 0 0 5 key
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:c:\miao_a\maxplus\zonghe\example_01\static_display.rpt
static_display
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
113 - - - 03 OUTPUT 0 1 0 0 q10
112 - - - 03 OUTPUT 0 1 0 0 q11
111 - - - 02 OUTPUT 0 1 0 0 q12
110 - - - 01 OUTPUT 0 1 0 0 q13
109 - - - 01 OUTPUT 0 1 0 0 q14
102 - - A -- OUTPUT 0 1 0 0 q15
101 - - A -- OUTPUT 0 1 0 0 q16
100 - - A -- OUTPUT 0 0 0 0 q17
122 - - - 12 OUTPUT 0 1 0 0 q20
121 - - - 10 OUTPUT 0 1 0 0 q21
120 - - - 09 OUTPUT 0 1 0 0 q22
119 - - - 08 OUTPUT 0 1 0 0 q23
118 - - - 07 OUTPUT 0 1 0 0 q24
117 - - - 06 OUTPUT 0 1 0 0 q25
116 - - - 05 OUTPUT 0 1 0 0 q26
114 - - - 04 OUTPUT 0 0 0 0 q27
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