logic.v

设计一个可编程间隔定时器

///////////////////////////////////////////////////////////////////////
//                                                                   //
// File name    : logic.v                                            //
// Title        :                                                    //
// Library      : WORK                                               //
//              :                                                    //
// Purpose      : according input to decide state                    //
//              :                                                    //
// Created On   : 2007-7-15                                          //
//              :                                                    //
// Comments     :                                                    //
//              :                                                    //
// Assumptions  : none                                               //
// Limitations  : none                                               //
// Known Errors : none                                               //
// Developers   : xl                                                 //
//              :                                                    //
// Notes        :                                                    // 
//                                                                   //
///////////////////////////////////////////////////////////////////////



module logic(
             //input
             rd,
             wr,
             a0,
             a1,
             rst_n,
             data_wr,
             //output
             state,
             byte_high,
             select_0,
             select_1,
             select_2
             );
  
  input  rd;
  input  wr;
  input  a0;
  input  a1;
  input  rst_n;
  input  [7:0] data_wr;
  output [2:0] state;
  output byte_high;
  output select_0;
  output select_1;
  output select_2;
    
  reg  [7:0] state;
  reg  byte_high_2;
  reg  byte_low_2;
  reg  byte_high_1;
  reg  byte_low_1;
  reg  byte_high_0;
  reg  byte_low_0;
  reg  byte_high;
  reg  byte_low;
  reg  select_0;
  reg  select_1;
  reg  select_2;
  reg  low;
  
  parameter state_load_counter_low=3'd1;
  parameter state_load_counter_high=3'd2;
  parameter state_write_mode_word=3'd3;
  parameter state_read_counter_latch=3'd4;
  parameter state_read_counter_low=3'd5;
  parameter state_read_counter_high=3'd6;
  parameter disable_3_state=3'd7;


  always @(rst_n or rd or wr or a1 or a0)
    if(rst_n) begin
      state = disable_3_state;
      low = 0;
      byte_high = 0;
      byte_low = 0;
      byte_high_0 = 0;
      byte_low_0 = 0;
      byte_high_1 = 0;
      byte_low_1 = 0;
      byte_high_2 = 0;
      byte_low_2 = 0;
      select_0 = 0;
      select_1 = 0;
      select_2 = 0;    
      end
    else
    case({rd,wr,a1,a0})
      5'b01000: if(low && byte_high) begin
                   state = state_load_counter_high;
                   low = 0;
                   end
                else if(byte_low) begin
                   state = state_load_counter_low;
                   if(byte_high) low = 1;
                   end
                else if(byte_high) 
                   state = state_load_counter_high;
                else 
                   state = disable_3_state;
      5'b01001: if(low && byte_high) begin
                   state = state_load_counter_high;
                   low = 0;
                   end
                else if(byte_low) begin
                   state = state_load_counter_low;
                   if(byte_high) low = 1;
                   end
                else if(byte_high) 
                   state = state_load_counter_high;
                else 
                   state = disable_3_state;
      5'b01010: if(low && byte_high) begin
                   state = state_load_counter_high;
                   low = 0;
                   end
                else if(byte_low) begin
                   state = state_load_counter_low;
                   if(byte_high) low = 1;
                   end
                else if(byte_high) 
                   state = state_load_counter_high;
                else 
                   state = disable_3_state;       
      5'b01011: begin
                  case(data_wr[7:6])
                    2'b00: begin
                             select_0 = 1;
                             select_1 = 0;
                             select_2 = 0;
                           end
                    2'b01: begin
                             select_0 = 0;
                             select_1 = 1;
                             select_2 = 0;
                           end
                    2'b10: begin
                             select_0 = 0;
                             select_1 = 0;
                             select_2 = 1;
                            end
                    default:begin
                              select_0 = 0;
                              select_1 = 0;
                              select_2 = 0;
                            end
                  endcase
                  byte_high = data_wr[5];
                  byte_low = data_wr[4];
                  if(!byte_low && !byte_high)begin
                    state = state_read_counter_latch;
                    end
                  else begin
                    state = state_write_mode_word;
                    case(data_wr[7:6])
                                   2'b00: begin
                                            byte_high_0 = byte_high;
                                            byte_low_0 = byte_low;
                                          end
                                   2'b01: begin
                                            byte_high_1 = byte_high;
                                            byte_low_1 = byte_low;
                                          end
                                   2'b10: begin
                                            byte_high_2 = byte_high;
                                            byte_low_2 = byte_low;
                                          end
                                 endcase
                    end
                end
      5'b00100: if(low && byte_high_0) begin
                  state = state_read_counter_high;
                  low = 0;
                  end
                else if(byte_low_0) begin
                  state = state_read_counter_low;
                  if(byte_high_0) low = 1;
                  end
                else if(byte_high_0)
                  state = state_read_counter_high;
                else
                  state = disable_3_state;
      5'b00101: if(low && byte_high_1) begin
                  state = state_read_counter_high;
                  low = 0;
                  end
                else if(byte_low_1) begin
                  state = state_read_counter_low;
                  if(byte_high_1) low = 1;
                  end
                else if(byte_high_1)
                  state = state_read_counter_high;
                else
                  state = disable_3_state;
      5'b00110: if(low && byte_high_2) begin
                  state = state_read_counter_high;
                  low = 0;
                  end
                else if(byte_low_2) begin
                  state = state_read_counter_low;
                  if(byte_high_2) low = 1;
                  end
                else if(byte_high_2)
                  state = state_read_counter_high;
                else
                  state = disable_3_state;
      default:  state = disable_3_state; 
    endcase
   
   endmodule