c8253.v

设计一个可编程间隔定时器

///////////////////////////////////////////////////////////////////////
//                                                                   //
// File name    : C8253.v                                            //
// Title        :                                                    //
// Library      : WORK                                               //
//              :                                                    //
// Purpose      : 8253 topfiles                                      //
//              :                                                    //
// Created On   : 2007-7-15                                          //
//              :                                                    //
// Comments     :                                                    //
//              :                                                    //
// Assumptions  : none                                               //
// Limitations  : none                                               //
// Known Errors : none                                               //
// Developers   : xl                                                 //
//              :                                                    //
// Notes        :                                                    // 
//                                                                   //
///////////////////////////////////////////////////////////////////////


///////////////////////////////////////////////////////////
//                                                       //
///////////////////////////////////////////////////////////
module  C8253(
              //input
              rst_n,
              rd,
              wr,
              a0,
              a1,
              clk_0,
              gate_0,
              clk_1,
              gate_1,
              clk_2,
              gate_2,
              //inout
              data,
              //output
              out_0,
              out_1,
              out_2,
            //  data_out,
              //data_rd_0,
              //data_rd_1,
              //data_rd_2,
              );

  input  rst_n;
  input  rd;
  input  wr;
  input  a0;
  input  a1;
  input  clk_0;
  input  gate_0;
  input  clk_1;
  input  gate_1;
  input  clk_2;
  input  gate_2;

  inout   [7:0]  data;
  output  out_0;
  output  out_1;
  output  out_2; 
  //output  [7:0] data_out;      
  //output  [7:0]  data_rd_0;
  //output  [7:0]  data_rd_1;
  //output  [7:0]  data_rd_2;
  
  wire [2:0] state;
  wire [7:0] data_wr;
  wire [7:0] data;        
  wire [7:0] data_rd_0;
  wire [7:0] data_rd_1;  
  wire [7:0] data_rd_2;
  wire select_0;
  wire select_1;
  wire select_2;
  wire load_counter_low;
  wire load_counter_high;
  wire load_over;
  wire latch_count;
  wire byte_high;
  wire read_counter_low;
  wire read_counter_high;
  wire control_write;
  wire out_0;
  wire out_1;
  wire out_2;
  wire rd;
  wire rst_n;
  wire wr; 
  wire clk_0;
  wire gate_0;
  wire clk_1;
  wire gate_1;
  wire clk_2;
  wire gate_2; 

  logic logic(
             //input
             .rd(rd),
             .wr(wr),
             .a0(a0),
             .a1(a1),
             .rst_n(rst_n),
             .data_wr(data),
             //output
             .state(state),
             .byte_high(byte_high),
             .select_0(select_0),
             .select_1(select_1),
             .select_2(select_2)
             );
   
	control control(
               //input
               .state(state),
               .byte_high(byte_high),
							  //output
               .load_counter_low(load_counter_low),
               .load_counter_high(load_counter_high),
               .load_over(load_over),
               .latch_count(latch_count),
               .read_counter_low(read_counter_low),
               .read_counter_high(read_counter_high),
               .control_write(control_write)
               ); 
               
	counter counter0(
               //input
               .select(select_0),
               .data_wr(data_wr),
               .load_counter_low(load_counter_low),
               .load_counter_high(load_counter_high),
               .load_over(load_over),
               .latch_count(latch_count),
               .read_counter_low(read_counter_low),
               .read_counter_high(read_counter_high),
               .control_write(control_write), 
               .gate(gate_0),
               .clk(clk_0),              
               //output
               .data_rd(data_rd_0),
               .out(out_0)
               ),
        counter1(
               //input
               .select(select_1),
               .data_wr(data_wr),
               .load_counter_low(load_counter_low),
               .load_counter_high(load_counter_high),
               .load_over(load_over),
               .latch_count(latch_count),
               .read_counter_low(read_counter_low),
               .read_counter_high(read_counter_high),
               .control_write(control_write), 
               .gate(gate_1),
               .clk(clk_1),              
               //output
               .data_rd(data_rd_1),
               .out(out_1)
               ),
        counter2(
               //input
               .select(select_2),
               .data_wr(data_wr),
               .load_counter_low(load_counter_low),
               .load_counter_high(load_counter_high),
               .load_over(load_over),
               .latch_count(latch_count),
               .read_counter_low(read_counter_low),
               .read_counter_high(read_counter_high),
               .control_write(control_write), 
               .gate(gate_2),
               .clk(clk_2),              
               //output
               .data_rd(data_rd_2),
               .out(out_2)
               );
   
   buffer buffer(
              .select_0(select_0),
              .select_1(select_1),
              .select_2(select_2),
              .data_rd_0(data_rd_0),
              .data_rd_1(data_rd_1),
              .data_rd_2(data_rd_2),
              .rd(rd),
              .wr(wr),
              //output
              .data_wr(data_wr),
              //inout
              .data(data)
            //  .data_out(data_out)
              );  
                                   
endmodule