dds_mcu.fit.qmsg

上传一个关于DDS开发的源程序

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.120 ns register register " "Info: Estimated most critical path is register to register delay of 1.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[21\] 1 REG LAB_X11_Y17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y17; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[21\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[21] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.738 ns) 1.120 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[22\] 2 REG LAB_X10_Y17 2 " "Info: 2: + IC(0.382 ns) + CELL(0.738 ns) = 1.120 ns; Loc. = LAB_X10_Y17; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[22\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.120 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[21] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[22] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 65.89 % " "Info: Total cell delay = 0.738 ns ( 65.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.382 ns 34.11 % " "Info: Total interconnect delay = 0.382 ns ( 34.11 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.120 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[21] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[22] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 01 11:38:32 2005 " "Info: Processing ended: Mon Aug 01 11:38:32 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0}  } {  } 0}