dds_mcu.map.qmsg

上传一个关于DDS开发的源程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 01 11:37:59 2005 " "Info: Processing started: Mon Aug 01 11:37:59 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off DDS_mcu -c DDS_mcu " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DDS_mcu -c DDS_mcu" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS_mcu.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDS_mcu.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDS_mcu " "Info: Found entity 1: DDS_mcu" {  } { { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "DFF_MCU.vhd 2 1 " "Info: Using design file DFF_MCU.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DFF_MCU-SYN " "Info: Found design unit 1: DFF_MCU-SYN" {  } { { "DFF_MCU.vhd" "" { Text "F:/chwb/DDS_MCU/DFF_MCU.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DFF_MCU " "Info: Found entity 1: DFF_MCU" {  } { { "DFF_MCU.vhd" "" { Text "F:/chwb/DDS_MCU/DFF_MCU.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus42/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus42/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 52 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "SR.vhd 2 1 " "Info: Using design file SR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SR-SYN " "Info: Found design unit 1: SR-SYN" {  } { { "SR.vhd" "" { Text "F:/chwb/DDS_MCU/SR.vhd" 56 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 SR " "Info: Found entity 1: SR" {  } { { "SR.vhd" "" { Text "F:/chwb/DDS_MCU/SR.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 43 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "99 " "Info: Implemented 99 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 01 11:38:08 2005 " "Info: Processing ended: Mon Aug 01 11:38:08 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0}  } {  } 0}