dds_mcu.tan.qmsg

上传一个关于DDS开发的源程序

{ "Info" "ITDB_TH_RESULT" "SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[31\] SS clock -0.714 ns register " "Info: th for register \"SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[31\]\" (data pin = \"SS\", clock pin = \"clock\") is -0.714 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { clock } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 16 24 192 32 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[31\] 2 REG LC_X10_Y17_N8 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X10_Y17_N8; Fanout = 1; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[31\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.485 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.683 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SS 1 CLK PIN_28 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 64; CLK Node = 'SS'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { SS } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 56 24 192 72 "SS" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.867 ns) 3.683 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[31\] 2 REG LC_X10_Y17_N8 1 " "Info: 2: + IC(1.347 ns) + CELL(0.867 ns) = 3.683 ns; Loc. = LC_X10_Y17_N8; Fanout = 1; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[31\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.214 ns" { SS SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 63.43 % " "Info: Total cell delay = 2.336 ns ( 63.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.347 ns 36.57 % " "Info: Total interconnect delay = 1.347 ns ( 36.57 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "3.683 ns" { SS SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "3.683 ns" { SS SS~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } { 0.000ns 0.000ns 1.347ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "3.683 ns" { SS SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "3.683 ns" { SS SS~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[31] } { 0.000ns 0.000ns 1.347ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 01 11:38:53 2005 " "Info: Processing ended: Mon Aug 01 11:38:53 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}