dds_mcu.tan.qmsg

上传一个关于DDS开发的源程序

{ "Info" "ITAN_NO_REG2REG_EXIST" "SS " "Info: No valid register-to-register data paths exist for clock \"SS\"" {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\] SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\] 275.03 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 275.03 MHz between source register \"SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\]\" and destination register \"SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.899 ns + Longest register register " "Info: + Longest register to register delay is 0.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\] 1 REG LC_X13_Y17_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y17_N7; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.115 ns) 0.899 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\] 2 REG LC_X12_Y17_N6 2 " "Info: 2: + IC(0.784 ns) + CELL(0.115 ns) = 0.899 ns; Loc. = LC_X12_Y17_N6; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "0.899 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 12.79 % " "Info: Total cell delay = 0.115 ns ( 12.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.784 ns 87.21 % " "Info: Total interconnect delay = 0.784 ns ( 87.21 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "0.899 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "0.899 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } { 0.000ns 0.784ns } { 0.000ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { clock } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 16 24 192 32 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\] 2 REG LC_X12_Y17_N6 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X12_Y17_N6; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[10\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.485 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { clock } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 16 24 192 32 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\] 2 REG LC_X13_Y17_N7 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y17_N7; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[9\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.485 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "0.899 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "0.899 ns" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } { 0.000ns 0.784ns } { 0.000ns 0.115ns } } } { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10] } {  } {  } } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] shiftin clock 4.070 ns register " "Info: tsu for register \"SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]\" (data pin = \"shiftin\", clock pin = \"clock\") is 4.070 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.987 ns + Longest pin register " "Info: + Longest pin to register delay is 6.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns shiftin 1 PIN PIN_214 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_214; Fanout = 1; PIN Node = 'shiftin'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { shiftin } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 96 24 192 112 "shiftin" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.397 ns) + CELL(0.115 ns) 6.987 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 2 REG LC_X13_Y17_N2 2 " "Info: 2: + IC(5.397 ns) + CELL(0.115 ns) = 6.987 ns; Loc. = LC_X13_Y17_N2; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "5.512 ns" { shiftin SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns 22.76 % " "Info: Total cell delay = 1.590 ns ( 22.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.397 ns 77.24 % " "Info: Total interconnect delay = 5.397 ns ( 77.24 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "6.987 ns" { shiftin SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "6.987 ns" { shiftin shiftin~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } { 0.000ns 0.000ns 5.397ns } { 0.000ns 1.475ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clock'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { clock } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 16 24 192 32 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 2 REG LC_X13_Y17_N2 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y17_N2; Fanout = 2; REG Node = 'SR:inst\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.485 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_shiftreg.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "6.987 ns" { shiftin SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "6.987 ns" { shiftin shiftin~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } { 0.000ns 0.000ns 5.397ns } { 0.000ns 1.475ns 0.115ns } } } { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { clock SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SS q\[0\] DFF_MCU:inst1\|lpm_ff:lpm_ff_component\|dffs\[0\] 8.028 ns register " "Info: tco from clock \"SS\" to destination pin \"q\[0\]\" through register \"DFF_MCU:inst1\|lpm_ff:lpm_ff_component\|dffs\[0\]\" is 8.028 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SS source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"SS\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SS 1 CLK PIN_28 64 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 64; CLK Node = 'SS'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { SS } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 56 24 192 72 "SS" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns DFF_MCU:inst1\|lpm_ff:lpm_ff_component\|dffs\[0\] 2 REG LC_X14_Y15_N2 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X14_Y15_N2; Fanout = 1; REG Node = 'DFF_MCU:inst1\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "1.485 ns" { SS DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { SS DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { SS SS~out0 DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "lpm_ff.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.850 ns + Longest register pin " "Info: + Longest register to pin delay is 4.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DFF_MCU:inst1\|lpm_ff:lpm_ff_component\|dffs\[0\] 1 REG LC_X14_Y15_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y15_N2; Fanout = 1; REG Node = 'DFF_MCU:inst1\|lpm_ff:lpm_ff_component\|dffs\[0\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "" { DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_ff.tdf" "" { Text "f:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf" 66 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.742 ns) + CELL(2.108 ns) 4.850 ns q\[0\] 2 PIN PIN_84 0 " "Info: 2: + IC(2.742 ns) + CELL(2.108 ns) = 4.850 ns; Loc. = PIN_84; Fanout = 0; PIN Node = 'q\[0\]'" {  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "4.850 ns" { DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] q[0] } "NODE_NAME" } "" } } { "DDS_mcu.bdf" "" { Schematic "F:/chwb/DDS_MCU/DDS_mcu.bdf" { { 80 656 832 96 "q\[31..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 43.46 % " "Info: Total cell delay = 2.108 ns ( 43.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.742 ns 56.54 % " "Info: Total interconnect delay = 2.742 ns ( 56.54 % )" {  } {  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "4.850 ns" { DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] q[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "4.850 ns" { DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] q[0] } { 0.000ns 2.742ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "2.954 ns" { SS DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "2.954 ns" { SS SS~out0 DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" "" { Report "F:/chwb/DDS_MCU/db/DDS_mcu_cmp.qrpt" Compiler "DDS_mcu" "UNKNOWN" "V1" "F:/chwb/DDS_MCU/db/DDS_mcu.quartus_db" { Floorplan "F:/chwb/DDS_MCU/" "" "4.850 ns" { DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] q[0] } "NODE_NAME" } "" } } { "f:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus42/bin/Technology_Viewer.qrui" "4.850 ns" { DFF_MCU:inst1|lpm_ff:lpm_ff_component|dffs[0] q[0] } { 0.000ns 2.742ns } { 0.000ns 2.108ns } } }  } 0}