dds_mcu.map.eqn

上传一个关于DDS开发的源程序

--operation mode is normal

D1_dffs[16]_lut_out = D1_dffs[15];
D1_dffs[16] = DFFEAS(D1_dffs[16]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[15] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[15]
--operation mode is normal

D1_dffs[15]_lut_out = D1_dffs[14];
D1_dffs[15] = DFFEAS(D1_dffs[15]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[14] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[14]
--operation mode is normal

D1_dffs[14]_lut_out = D1_dffs[13];
D1_dffs[14] = DFFEAS(D1_dffs[14]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[13] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[13]
--operation mode is normal

D1_dffs[13]_lut_out = D1_dffs[12];
D1_dffs[13] = DFFEAS(D1_dffs[13]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[12] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[12]
--operation mode is normal

D1_dffs[12]_lut_out = D1_dffs[11];
D1_dffs[12] = DFFEAS(D1_dffs[12]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[11] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[11]
--operation mode is normal

D1_dffs[11]_lut_out = D1_dffs[10];
D1_dffs[11] = DFFEAS(D1_dffs[11]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[10] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[10]
--operation mode is normal

D1_dffs[10]_lut_out = D1_dffs[9];
D1_dffs[10] = DFFEAS(D1_dffs[10]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[9] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[9]
--operation mode is normal

D1_dffs[9]_lut_out = D1_dffs[8];
D1_dffs[9] = DFFEAS(D1_dffs[9]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[8] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[8]
--operation mode is normal

D1_dffs[8]_lut_out = D1_dffs[7];
D1_dffs[8] = DFFEAS(D1_dffs[8]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[7] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[7]
--operation mode is normal

D1_dffs[7]_lut_out = D1_dffs[6];
D1_dffs[7] = DFFEAS(D1_dffs[7]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[6] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[6]
--operation mode is normal

D1_dffs[6]_lut_out = D1_dffs[5];
D1_dffs[6] = DFFEAS(D1_dffs[6]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[5] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[5]
--operation mode is normal

D1_dffs[5]_lut_out = D1_dffs[4];
D1_dffs[5] = DFFEAS(D1_dffs[5]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[4] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[4]
--operation mode is normal

D1_dffs[4]_lut_out = D1_dffs[3];
D1_dffs[4] = DFFEAS(D1_dffs[4]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[3] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[3]
--operation mode is normal

D1_dffs[3]_lut_out = D1_dffs[2];
D1_dffs[3] = DFFEAS(D1_dffs[3]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[2] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[2]
--operation mode is normal

D1_dffs[2]_lut_out = D1_dffs[1];
D1_dffs[2] = DFFEAS(D1_dffs[2]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[1] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[1]
--operation mode is normal

D1_dffs[1]_lut_out = D1_dffs[0];
D1_dffs[1] = DFFEAS(D1_dffs[1]_lut_out, clock, VCC, , !SS, , , , );


--D1_dffs[0] is SR:inst|lpm_shiftreg:lpm_shiftreg_component|dffs[0]
--operation mode is normal

D1_dffs[0]_lut_out = shiftin;
D1_dffs[0] = DFFEAS(D1_dffs[0]_lut_out, clock, VCC, , !SS, , , , );


--SS is SS
--operation mode is input

SS = INPUT();


--clock is clock
--operation mode is input

clock = INPUT();


--shiftin is shiftin
--operation mode is input

shiftin = INPUT();


--q[31] is q[31]
--operation mode is output

q[31] = OUTPUT(E1_dffs[31]);


--q[30] is q[30]
--operation mode is output

q[30] = OUTPUT(E1_dffs[30]);


--q[29] is q[29]
--operation mode is output

q[29] = OUTPUT(E1_dffs[29]);


--q[28] is q[28]
--operation mode is output

q[28] = OUTPUT(E1_dffs[28]);


--q[27] is q[27]
--operation mode is output

q[27] = OUTPUT(E1_dffs[27]);


--q[26] is q[26]
--operation mode is output

q[26] = OUTPUT(E1_dffs[26]);


--q[25] is q[25]
--operation mode is output

q[25] = OUTPUT(E1_dffs[25]);


--q[24] is q[24]
--operation mode is output

q[24] = OUTPUT(E1_dffs[24]);


--q[23] is q[23]
--operation mode is output

q[23] = OUTPUT(E1_dffs[23]);


--q[22] is q[22]
--operation mode is output

q[22] = OUTPUT(E1_dffs[22]);


--q[21] is q[21]
--operation mode is output

q[21] = OUTPUT(E1_dffs[21]);


--q[20] is q[20]
--operation mode is output

q[20] = OUTPUT(E1_dffs[20]);


--q[19] is q[19]
--operation mode is output

q[19] = OUTPUT(E1_dffs[19]);


--q[18] is q[18]
--operation mode is output

q[18] = OUTPUT(E1_dffs[18]);


--q[17] is q[17]
--operation mode is output

q[17] = OUTPUT(E1_dffs[17]);


--q[16] is q[16]
--operation mode is output

q[16] = OUTPUT(E1_dffs[16]);


--q[15] is q[15]
--operation mode is output

q[15] = OUTPUT(E1_dffs[15]);


--q[14] is q[14]
--operation mode is output

q[14] = OUTPUT(E1_dffs[14]);


--q[13] is q[13]
--operation mode is output

q[13] = OUTPUT(E1_dffs[13]);


--q[12] is q[12]
--operation mode is output

q[12] = OUTPUT(E1_dffs[12]);


--q[11] is q[11]
--operation mode is output

q[11] = OUTPUT(E1_dffs[11]);


--q[10] is q[10]
--operation mode is output

q[10] = OUTPUT(E1_dffs[10]);


--q[9] is q[9]
--operation mode is output

q[9] = OUTPUT(E1_dffs[9]);


--q[8] is q[8]
--operation mode is output

q[8] = OUTPUT(E1_dffs[8]);


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(E1_dffs[7]);


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(E1_dffs[6]);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(E1_dffs[5]);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(E1_dffs[4]);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(E1_dffs[3]);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(E1_dffs[2]);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(E1_dffs[1]);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(E1_dffs[0]);