dds_mcu.map.rpt

上传一个关于DDS开发的源程序

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                         ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------+
; Compilation Hierarchy Node                  ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                  ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------+
; |DDS_mcu                                    ; 64 (0)      ; 64           ; 0           ; 35   ; 0            ; 0 (0)        ; 64 (0)            ; 0 (0)            ; 0 (0)           ; |DDS_mcu                                             ;
;    |DFF_MCU:inst1|                          ; 32 (0)      ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (0)            ; 0 (0)            ; 0 (0)           ; |DDS_mcu|DFF_MCU:inst1                               ;
;       |lpm_ff:lpm_ff_component|             ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |DDS_mcu|DFF_MCU:inst1|lpm_ff:lpm_ff_component       ;
;    |SR:inst|                                ; 32 (0)      ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (0)            ; 0 (0)            ; 0 (0)           ; |DDS_mcu|SR:inst                                     ;
;       |lpm_shiftreg:lpm_shiftreg_component| ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |DDS_mcu|SR:inst|lpm_shiftreg:lpm_shiftreg_component ;
+---------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/chwb/DDS_MCU/DDS_mcu.map.eqn.


+-------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                            ;
+----------------------------------+-----------------+--------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                 ;
+----------------------------------+-----------------+--------------------------------------------------------------+
; DDS_mcu.bdf                      ; yes             ; F:/chwb/DDS_MCU/DDS_mcu.bdf                                  ;
; DFF_MCU.vhd                      ; yes             ; F:/chwb/DDS_MCU/DFF_MCU.vhd                                  ;
; lpm_ff.tdf                       ; yes             ; f:/altera/quartus42/libraries/megafunctions/lpm_ff.tdf       ;
; lpm_constant.inc                 ; yes             ; f:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; aglobal42.inc                    ; yes             ; f:/altera/quartus42/libraries/megafunctions/aglobal42.inc    ;
; SR.vhd                           ; yes             ; F:/chwb/DDS_MCU/SR.vhd                                       ;
; lpm_shiftreg.tdf                 ; yes             ; f:/altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf ;
; dffeea.inc                       ; yes             ; f:/altera/quartus42/libraries/megafunctions/dffeea.inc       ;
+----------------------------------+-----------------+--------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Logic cells                     ; 64        ;
; Total combinational functions   ; 0         ;
; Total 4-input functions         ; 0         ;
; Total 3-input functions         ; 0         ;
; Total 2-input functions         ; 0         ;
; Total 1-input functions         ; 0         ;
; Total 0-input functions         ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 64        ;
; I/O pins                        ; 35        ;
; Maximum fan-out node            ; SS        ;
; Maximum fan-out                 ; 64        ;
; Total fan-out                   ; 192       ;
; Average fan-out                 ; 1.94      ;
+---------------------------------+-----------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 64    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 0     ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 64    ;
; Number of cells with combinational logic only          ; 0     ;
; Number of cells with registers only                    ; 64    ;
; Number of cells with combinational logic and registers ; 0     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 64    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Aug 01 11:37:59 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DDS_mcu -c DDS_mcu
Info: Found 1 design units, including 1 entities, in source file DDS_mcu.bdf
    Info: Found entity 1: DDS_mcu
Info: Using design file DFF_MCU.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: DFF_MCU-SYN
    Info: Found entity 1: DFF_MCU
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus42/libraries/megafunctions/lpm_ff.tdf
    Info: Found entity 1: lpm_ff
Info: Using design file SR.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: SR-SYN
    Info: Found entity 1: SR
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus42/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Implemented 99 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 32 output pins
    Info: Implemented 64 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Aug 01 11:38:08 2005
    Info: Elapsed time: 00:00:11