pcic_pg.tdf

PCI logicore,在某网站上下载的ip核文件

-- File Name: pcic_pg.tdf
-- Function	:  	This is used to generate parity on the PCI Data/Command bus
--			This uses carry chains for the Command/Byte Enable bits
--			to meet setup time on cben[3..0]
-- Author	: Ziad M. Abu-Lebdeh
-- Rev History
--	6/97	Initial Entry
--
--	$History: pcic_pg.tdf $
-- 
-- *****************  Version 58  *****************
-- User: Otan         Date: 6/14/99    Time: 1:15p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized frame_or and req64_or for setup
-- 
-- *****************  Version 57  *****************
-- User: Otan         Date: 5/11/99    Time: 4:14p
-- Updated in $/MegaCore/HandOff/45/source/src
-- DAC back; after version1.01
-- 
-- *****************  Version 55  *****************
-- User: Otan         Date: 3/14/99    Time: 8:59a
-- Updated in $/MegaCore/HandOff/45/source/src
-- pre1.0-2
-- 
-- *****************  Version 54  *****************
-- User: Otan         Date: 3/02/99    Time: 10:24a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Simulations work
-- 
-- *****************  Version 53  *****************
-- User: Otan         Date: 2/26/99    Time: 6:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed fast_back-to-back
-- 
-- *****************  Version 52  *****************
-- User: Otan         Date: 2/26/99    Time: 11:53a
-- Updated in $/MegaCore/HandOff/45/source/src
-- MS_REQ Optimization fixed
-- 
-- *****************  Version 50  *****************
-- User: Otan         Date: 2/17/99    Time: 5:13p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 49  *****************
-- User: Otan         Date: 2/16/99    Time: 7:56p
-- Updated in $/MegaCore/HandOff/45/source/src
-- master write simulations
-- 
-- *****************  Version 48  *****************
-- User: Otan         Date: 2/09/99    Time: 8:58a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Updated for Master Read simulations. 2/9/99
-- 
-- *****************  Version 47  *****************
-- User: Otan         Date: 2/02/99    Time: 2:11p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 46  *****************
-- User: Otan         Date: 2/02/99    Time: 1:07p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Updated master parity error
-- 
-- *****************  Version 45  *****************
-- User: Otan         Date: 1/29/99    Time: 11:59a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Been Optimized to meet 33MHz performance.
-- 
-- *****************  Version 44  *****************
-- User: Otan         Date: 1/28/99    Time: 8:31a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master and Target Optimizations.  These files are before we changed
-- ador_hi_dena in pcic_t.tdf.
-- 
-- *****************  Version 43  *****************
-- User: Otan         Date: 1/27/99    Time: 9:08a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target and Master Optimizations
-- 
-- *****************  Version 42  *****************
-- User: Otan         Date: 1/25/99    Time: 10:43a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Optimization
-- 
-- *****************  Version 41  *****************
-- User: Otan         Date: 1/21/99    Time: 4:26p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Write and Read have been extensively simulated
-- 
-- *****************  Version 40  *****************
-- User: Otan         Date: 12/24/98   Time: 12:49p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 39  *****************
-- User: Otan         Date: 12/22/98   Time: 4:27p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixing wait states for each data phase
-- 
-- *****************  Version 38  *****************
-- User: Otan         Date: 12/16/98   Time: 7:33a
-- Updated in $/MegaCore/HandOff/45/source/src
-- for beta release
-- 
-- *****************  Version 36  *****************
-- User: Otan         Date: 12/16/98   Time: 6:50a
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 34  *****************
-- User: Otan         Date: 12/15/98   Time: 9:29p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 33  *****************
-- User: Otan         Date: 12/14/98   Time: 11:17p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 32  *****************
-- User: Otan         Date: 12/08/98   Time: 4:59p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 31  *****************
-- User: Otan         Date: 12/07/98   Time: 8:23p
-- Updated in $/MegaCore/HandOff/45/source/src
-- ZMA- I checked this in on OT machine without figureing out what are the
-- changes.
-- 
-- *****************  Version 30  *****************
-- User: Nprasad      Date: 12/03/98   Time: 6:16p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 29  *****************
-- User: Nprasad      Date: 11/30/98   Time: 5:53p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments to all the files. I'M DONE!! I'M DONE!!
-- 
-- *****************  Version 28  *****************
-- User: Nprasad      Date: 11/30/98   Time: 3:36p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the Master Write State Machine and the relevant signals to the
-- new specification. Ran simulations and fixed several bugs.
-- 
-- *****************  Version 27  *****************
-- User: Nprasad      Date: 11/29/98   Time: 4:24p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added capability to indicate a pure 64 bit system to. Parameter
-- 64bit_system.
-- 
-- *****************  Version 26  *****************
-- User: Nprasad      Date: 11/29/98   Time: 3:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed lm_ack, irdy, frame and req64 to meet the new specifications
-- and logic. Also added lm_req32 as a control signal to trigger the
-- master core to request the bus.
-- 
-- *****************  Version 25  *****************
-- User: Nprasad      Date: 11/29/98   Time: 2:31p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write State Machine is now changed  to the new specification. It
-- suports:
-- 32 bit burst through lm_req32
-- 32 bit single cycle
-- 32 bit io cycle
-- 64 bit burst
-- 64 bit single cycle <-- Only if the bus contains exclusively 64 bit
-- devices
-- 
-- *****************  Version 24  *****************
-- User: Nprasad      Date: 11/25/98   Time: 4:56p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments.
-- 
-- *****************  Version 23  *****************
-- User: Otan         Date: 11/25/98   Time: 1:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write Simulations Work. 
-- 
-- *****************  Version 22  *****************
-- User: Nprasad      Date: 11/24/98   Time: 4:02p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Checked the Master Write State Machine
-- 
-- *****************  Version 21  *****************
-- User: Otan         Date: 11/23/98   Time: 7:04p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write debugging 64-64 and 32-64.
-- 
-- *****************  Version 20  *****************
-- User: Otan         Date: 11/23/98   Time: 3:50p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Simulations successful.  Added 64-bit -> 64-bit and 32-bit
-- -> 64-bit transactions.
-- 
-- *****************  Version 19  *****************
-- User: Nprasad      Date: 11/23/98   Time: 11:32a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed 32-->64 State Machine in Target.
-- 
-- *****************  Version 18  *****************
-- User: Otan         Date: 11/23/98   Time: 10:19a
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 17  *****************
-- User: Otan         Date: 11/20/98   Time: 7:21p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Read Debugging
-- 
-- *****************  Version 16  *****************
-- User: Otan         Date: 11/20/98   Time: 4:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Write and Memory Read works with simulation, local and
-- PCI wait states.
-- Added l_ldata_ackn and l_hdata_ackn to distinguish low and high dwords
-- for 32-bit PCI. 
-- 
-- *****************  Version 15  *****************
-- User: Otan         Date: 11/19/98   Time: 1:55p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 32-bit finished, except for data timeout.
-- 
-- *****************  Version 14  *****************
-- User: Otan         Date: 11/18/98   Time: 7:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read/Write works for single and burst cycles for PCI and local
-- wait states.
-- 
-- *****************  Version 13  *****************
-- User: Otan         Date: 11/17/98   Time: 10:27p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read simulating successfully, except for lm_ackn
-- 
-- *****************  Version 12  *****************
-- User: Nprasad      Date: 11/17/98   Time: 8:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added 64 bit place holders for all of the files. Completed par gen and
-- parity check for 64 bit. 
-- 
-- *****************  Version 11  *****************
-- User: Nprasad      Date: 11/16/98   Time: 10:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed Master Datapath to the top level. Added the extra signals
-- needed.
-- 
-- *****************  Version 10  *****************
-- User: Otan         Date: 11/16/98   Time: 2:44p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Hold Registers Implemented.  
-- Changed the ad_ce_nc=trg_ador_ena.  
-- Target Read/Write single and burst cycle simulations with local and PCI
-- wait states successful. 
-- 
-- *****************  Version 9  *****************
-- User: Otan         Date: 11/15/98   Time: 10:36p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 8  *****************
-- User: Otan         Date: 11/14/98   Time: 7:13p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Working on Master Read
-- 
-- *****************  Version 7  *****************
-- User: Otan         Date: 11/14/98   Time: 1:12p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Successfully Simulated with Local and PCI wait states.
-- 
-- *****************  Version 6  *****************
-- User: Otan         Date: 11/13/98   Time: 6:00p
-- Updated in $/MegaCore/HandOff/45/source/src
-- target read successfully simulated.
-- 
-- *****************  Version 5  *****************
-- User: Nprasad      Date: 11/12/98   Time: 11:49p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the output data path to the top level. Change the CE for the
-- input Ad registers so that data and command are till the next cycle.
-- Changed the Target local read state machine and the rest of the signals
-- to adjust for the change in the datapath. First draft for target local
-- read. Minor tweaks elsewhere.
-- 
-- *****************  Version 4  *****************
-- User: Nprasad      Date: 11/11/98   Time: 10:28p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target local write data path complete. Target local write state machine
-- complete. Signals were modified to fucntion as specified. First draft.
-- 
-- *****************  Version 3  *****************
-- User: Nprasad      Date: 11/11/98   Time: 7:11p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Address path has changed. Data path is through a partial change. 
-- New signal names added. Other superficial changes. 
-- 
-- *****************  Version 2  *****************
-- User: Nprasad      Date: 10/26/98   Time: 11:42a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Removed PCI_B Comments and Optmization
-- 
-- *****************  Version 1  *****************
-- User: Ziada        Date: 10/22/98   Time: 4:34p
-- Created in $/MegaCore/HandOff/45/source/src
-- 
-- *****************  Version 7  *****************
-- User: Ziada        Date: 9/10/98    Time: 9:12a
-- Updated in $/MegaCore/HandOff/35/source/src
-- Changed Name of files
-- 

SUBDESIGN pcic_pg
	(data[31..0]	: INPUT;
	cbeN[3..0]		: INPUT;
	parity		: OUTPUT;
)

VARIABLE
	par[9..0]		: LCELL;
	parc[11..10] 	: NODE ;
 	

BEGIN

  -- Parity generation equations
  par0 = data0 $ data1 $ data2 $ data3;
  par1 = data4 $ data5 $ data6 $ data7;
  par2 = data8 $ data9 $ data10 $ data11;
  par3 = data12 $ data13 $ data14 $ data15;
  par4 = data16 $ data17 $ data18 $ data19;
  par5 = data20 $ data21 $ data22 $ data23;
  par6 = data24 $ data25 $ data26 $ data27;
  par7 = data28 $ data29 $ data30 $ data31;
  par8 = par0 $ par1 $ par2 $ par3;
  par9 = par4 $ par5 $ par6 $ par7;
  
  parc10 = CARRY(par8 $par9);
  parc11 = CARRY( parc10 $ cbeN3 $ cbeN2);
  parity = parc11 $ cbeN1 $ cbeN0 ;
  

end ;