pcic_cd.tdf

PCI logicore,在某网站上下载的ip核文件

-- File Name: pcic_cd.tdf
-- Function	: Optimized Address decoder for Configuration Space accesses
-- Author	: Ziad M. Abu-Lebdeh
-- Rev History
--	6/97	Initial Entry
--
--	$History: pcic_cd.tdf $
-- 
-- *****************  Version 13  *****************
-- User: Otan         Date: 6/14/99    Time: 1:15p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized frame_or and req64_or for setup
-- 
-- *****************  Version 12  *****************
-- User: Otan         Date: 5/11/99    Time: 4:14p
-- Updated in $/MegaCore/HandOff/45/source/src
-- DAC back; after version1.01
-- 
-- *****************  Version 10  *****************
-- User: Jmessavu     Date: 5/10/99    Time: 7:50a
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added support for the hardwire bars.   Change the use_exp_rom_default
-- parameter to exp_rom_default_ena.
-- 
-- *****************  Version 9  *****************
-- User: Ziada        Date: 1/22/99    Time: 12:07p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Updated files for Joseph Impastata 
-- 
-- *****************  Version 8  *****************
-- User: Ziada        Date: 1/08/99    Time: 5:00p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added Expansion ROM BAR
-- Changed CAP_PTR_ENA to be Text Value insted of Decimal
-- 
-- *****************  Version 7  *****************
-- User: Otan         Date: 10/12/98   Time: 12:23p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added the capabilities list at address 34H in the configuration space
-- 
-- *****************  Version 6  *****************
-- User: Ziada        Date: 9/10/98    Time: 9:12a
-- Updated in $/MegaCore/HandOff/35/source/src
-- Changed Name of files
-- 
-- *****************  Version 5  *****************
-- User: Brians       Date: 4/27/98    Time: 12:42p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Optimized for 10K30A-1
-- 
-- *****************  Version 4  *****************
-- User: Ziada        Date: 2/05/98    Time: 11:11a
-- Updated in $/MegaCore/HandOff/36/source/src
-- Code First cut.
-- 
-- *****************  Version 2  *****************
-- User: Ziada        Date: 9/23/97    Time: 11:35a
-- Updated in $/MegaCore/HandOff/40/src
-- Added History Statement to Header
--
--


SUBDESIGN 'pcic_cd'
(
	clk			: INPUT;	-- PCI Clock
	rstn			: INPUT;	-- PCI Reset
	ena			: INPUT;	-- Clock Enable
	dat[5..0]		: INPUT;	-- Data Input
	
	dec0R			: OUTPUT;	-- Data = B"000000"	-- 00H	Dev ID
	dec1R			: OUTPUT;	-- Data = B"000001"	-- 04H	CMD
	dec2R			: OUTPUT;	-- Data = B"000010"	-- 08H	Rev ID
	dec3R			: OUTPUT;	-- Data = B"000011"	-- 0CH	Cache
	dec4R			: OUTPUT;	-- Data = B"000100"	-- 10H	BAR0
	dec5R			: OUTPUT;	-- Data = B"000101"	-- 14H	BAR1	
	dec6R			: OUTPUT;	-- Data = B"000110"	-- 18H	BAR2
	dec7R			: OUTPUT;	-- Data = B"000111"	-- 1CH	BAR3
	dec8R			: OUTPUT;	-- Data = B"001000"	-- 20H	BAR4
	dec9R			: OUTPUT;	-- Data = B"001001"	-- 24H	BAR5
	dec10R			: OUTPUT; 	-- Data = B"001010"	-- 28H	CIS	
 	dec11R			: OUTPUT;	-- Data = B"001011" -- 2CH	SUBS
	dec12R			: OUTPUT;	-- Data = B"001100"	-- 30H	EXP ROM
 	dec13R			: OUTPUT;	-- Data = B"001101"	-- 34H	CAP PTR
-- 	dec14R			: OUTPUT; 	-- Data = B"001110"	-- 38H	Reserved
 	dec15R			: OUTPUT; 	-- Data = B"001111" -- 3CH	Int
-- 	dec16R			: OUTPUT; 	-- Data = B"010000" -- 40H


--	dec11R		: OUTPUT;	-- Data = B"001100"
--	dec15R		: OUTPUT;	-- Data = B"001111"

)

VARIABLE

	
--	decR[11..0]		: DFFE;	-- Output Registers
--	decR_d[11..0] 	: NODE;	-- Register D Inputs
	decR[15..0]		: DFFE;	-- Output Registers
	decR_d[15..0] 	: NODE;	-- Register D Inputs
	dec_up[3..0]	: LCELL;	-- Upper Bits Decode LCELLS
	
	junk			: NODE;	-- This is a junk node to prevent warnings
	
		
BEGIN

	dec_up0	= !dat5 and !dat4 and !dat3 and !dat2;
	dec_up1	= !dat5 and !dat4 and !dat3 and dat2;
	dec_up2	= !dat5 and !dat4 and dat3  and !dat2;
	dec_up3	= !dat5 and !dat4 and dat3  and dat2;
--	dec_up4 	= !dat5 and dat4  and !dat3 and !dat2;

	decR_d0		= dec_up0 and !dat1 and !dat0;  		-- Address = "00000000"	-- 00H 	Dev ID
	decR_d1		= dec_up0 and !dat1 and dat0;			-- Address = "00000100"	-- 04H 	CMD
	decR_d2		= dec_up0 and dat1 	and !dat0;			-- Address = "00001000"	-- 08H	Rev ID
	decR_d3		= dec_up0 and dat1 	and dat0;			-- Address = "00001100"	-- 0CH	Cache
	decR_d4		= dec_up1 and !dat1 and !dat0;			-- Address = "00010000"	-- 10H 	BAR0
	decR_d5		= dec_up1 and !dat1 and dat0;			-- Address = "00010100"	-- 14H	BAR1	
	decR_d6		= dec_up1 and dat1 	and !dat0;			-- Address = "00011000"	-- 18H	BAR2
	decR_d7		= dec_up1 and dat1 	and dat0;			-- Address = "00011100"	-- 1CH	BAR3
	decR_d8		= dec_up2 and !dat1 and !dat0;			-- Address = "00100000"	-- 20H	BAR4
	decR_d9		= dec_up2 and !dat1 and dat0;			-- Address = "00100100"	-- 24H	BAR5
	decR_d10	= dec_up2 and dat1 	and !dat0;			-- Address = "00101100"	-- 28H	CIS	
	decR_d11  	= dec_up2 and dat1 	and dat0; 			-- Address = "00110100" -- 2CH	SUBS
	decR_d12	= dec_up3 and !dat1	and !dat0;			-- Address = "00111100"	-- 30H	EXP ROM
	decR_d13	= dec_up3 and !dat1	and dat0;			-- Address = "00110000"	-- 34H	CAP PTR
	decR_d14	= dec_up3 and dat1	and !dat0;			-- Address = "00110000"	-- 38H	Reserved
	decR_d15	= dec_up3 and dat1	and dat0;			-- Address = "00110000"	-- 3CH	Int
--	decR_d16	= dec_up4 and !dat1	and !dat0;			-- Address = "00110000"	-- 40H
	
--	decR_d11	= dec_up3 and dat1 and dat0;			-- Address = "00111100"	-- 3CH
--	decR_d12  = dec_up4 and !dat1 and !dat0;			-- Address = "01000000"  -- 40H

	decR[]	= decR_d[];
	decR[].clk	= clk;
	decR[].clrn = rstn;
	decR[].ENA	= ena;
	

	dec0R		= decR0;
	dec1R		= decR1;
	dec2R		= decR2;
	dec3R		= decR3;
	dec4R		= decR4;
	dec5R		= decR5;
	dec6R		= decR6;
	dec7R		= decR7;
	dec8R		= decR8;
	dec9R		= decR9;
	dec10R		= decR10;
	
	dec11R		= decR11;
	dec12R		= decR12;
	dec13R   	= decR13;
--	dec14R		= decR14;
	dec15R		= decR15;

	junk		= junk or decR14;
-- 	dec15R	= decR11;
--	dec16R	= decR12;
	
END ;