📄 pcic_pk.tdf
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-- Changed Name of the perr_det_set to perr_set_detR
--
SUBDESIGN 'pcic_pk'
(
clk : INPUT; -- PCI clk Input
rstn : INPUT; -- PCI rstn Input
par : INPUT; -- PCI par signal
trg_64_trans_out : INPUT;
mstr_64_trans_out : INPUT;
--jot trg_adr_phase_out : INPUT;
--jot lm_adr_ackn : INPUT;
low_ad_IR_addr[31..0] : INPUT; -- PCI AD Bus Input Registers
low_cben_IR_addr[3..0] : INPUT; -- PCI CBEN Bus Input Registers
low_ad_IR[31..0] : INPUT; -- PCI AD Bus Input Registers
low_cben_IR[3..0] : INPUT; -- PCI CBEN Bus Input Registers
par64 : INPUT; -- PCI par signal
high_ad_IR[31..0] : INPUT; -- PCI AD Bus Input Registers
high_cben_IR[3..0] : INPUT; -- PCI CBEN Bus Input Registers
perr_ena : INPUT; -- Configuration Command Register Parity Enable
serr_ena : INPUT; -- Configuration Command Register System Error Enable
mstr_perr_vld : INPUT; -- Master Data Parity error valid
targ_perr_vld : INPUT; -- Target Data Parity error Valid
targ_serr_vld : INPUT; -- Target System Error valid
perr_det_set : OUTPUT; -- PERR Detect Set, Config Status Register Bit 15 Set
serr_sig_set : OUTPUT; -- System Error Signaled Set
perr_out : OUTPUT; -- Parity Error Output
serr_out : OUTPUT; -- System Error Output
)
VARIABLE
perr_det_setR_r1 : DFFE; -- Parity Error Detect Set SR15 Set
perr_det_setR_r2 : DFFE; -- Parity Error Detect Set SR15 Set
perr_det_setR_r3 : DFFE; -- Parity Error Detect Set SR15 Set
perr_det_setR_r1_d : NODE; -- Parity Error Detect Set SR15 Set
perr_det_setR_r2_d : NODE; -- Parity Error Detect Set SR15 Set
perr_det_setR_r3_d : NODE; -- Parity Error Detect Set SR15 Set
perr_det_setR : NODE;
-- perr_rep_set : DFFE; -- Parity Error Report Set SR8 Set
-- serr_sig_set : DFFE; -- System Error Signaled Set SR14 Set
-- xor_chk : xor_36; -- Parity Checker XOR Tree
xor_chk_out : NODE; -- Parity Checker XOR Tree Output
xor_chk_out64 : NODE; -- Parity Checker XOR Tree Output
xor_chk_outad : NODE; -- Parity Checker XOR Tree Output
-- par_error_stat : NODE; -- Par error detected
-- par_error_perr : NODE; -- Par error detected
par_error_serr : NODE; -- Par error detected
par_error : NODE;
par_error64 : NODE;
perr_OR : NODE; -- Perr Output Register
perr_OR_not : DFFE; -- Perr Output Register
perr_OR_not_lc1 : NODE;
perr_OR_not_lc2 : NODE;
perr_OR_not_lc3 : NODE;
serr_OR : DFFE; -- Serr Output Register
serr_or_lc : NODE;
xxlad[11..0] : LCELL; -- Intermediate XOR Gates
xxl[11..0] : LCELL; -- Intermediate XOR Gates
xxh[11..0] : LCELL; -- Intermediate XOR Gates
BEGIN
-- Parity generation equations for the lower data
xxlad0 = low_ad_IR_addr0 $ low_ad_IR_addr1 $ low_ad_IR_addr2 $ low_ad_IR_addr3;
xxlad1 = low_ad_IR_addr4 $ low_ad_IR_addr5 $ low_ad_IR_addr6 $ low_ad_IR_addr7;
xxlad2 = low_ad_IR_addr8 $ low_ad_IR_addr9 $ low_ad_IR_addr10 $ low_ad_IR_addr11;
xxlad3 = low_ad_IR_addr12 $ low_ad_IR_addr13 $ low_ad_IR_addr14 $ low_ad_IR_addr15;
xxlad4 = low_ad_IR_addr16 $ low_ad_IR_addr17 $ low_ad_IR_addr18 $ low_ad_IR_addr19;
xxlad5 = low_ad_IR_addr20 $ low_ad_IR_addr21 $ low_ad_IR_addr22 $ low_ad_IR_addr23;
xxlad6 = low_ad_IR_addr24 $ low_ad_IR_addr25 $ low_ad_IR_addr26 $ low_ad_IR_addr27;
xxlad7 = low_ad_IR_addr28 $ low_ad_IR_addr29 $ low_ad_IR_addr30 $ low_ad_IR_addr31;
xxlad8 = low_cben_IR_addr0 $ low_cben_IR_addr1 $ low_cben_IR_addr2 $ low_cben_IR_addr3;
xxlad9 = xxlad0 $ xxlad1 $ xxlad2 $ xxlad3;
xxlad10 = xxlad4 $ xxlad5 $ xxlad6 $ xxlad7;
xxlad11 = xxlad8 $ xxlad9 $ xxlad10;
xor_chk_outad = xxlad11 ;
-- Parity generation equations for the lower data
xxl0 = low_ad_IR0 $ low_ad_IR1 $ low_ad_IR2 $ low_ad_IR3;
xxl1 = low_ad_IR4 $ low_ad_IR5 $ low_ad_IR6 $ low_ad_IR7;
xxl2 = low_ad_IR8 $ low_ad_IR9 $ low_ad_IR10 $ low_ad_IR11;
xxl3 = low_ad_IR12 $ low_ad_IR13 $ low_ad_IR14 $ low_ad_IR15;
xxl4 = low_ad_IR16 $ low_ad_IR17 $ low_ad_IR18 $ low_ad_IR19;
xxl5 = low_ad_IR20 $ low_ad_IR21 $ low_ad_IR22 $ low_ad_IR23;
xxl6 = low_ad_IR24 $ low_ad_IR25 $ low_ad_IR26 $ low_ad_IR27;
xxl7 = low_ad_IR28 $ low_ad_IR29 $ low_ad_IR30 $ low_ad_IR31;
xxl8 = low_cbeN_IR0 $ low_cbeN_IR1 $ low_cbeN_IR2 $ low_cbeN_IR3;
xxl9 = xxl0 $ xxl1 $ xxl2 $ xxl3;
xxl10 = xxl4 $ xxl5 $ xxl6 $ xxl7;
xxl11 = xxl8 $ xxl9 $ xxl10;
xor_chk_out = xxl11 ;
-- Parity generation equations for the upper data
xxh0 = high_ad_IR0 $ high_ad_IR1 $ high_ad_IR2 $ high_ad_IR3;
xxh1 = high_ad_IR4 $ high_ad_IR5 $ high_ad_IR6 $ high_ad_IR7;
xxh2 = high_ad_IR8 $ high_ad_IR9 $ high_ad_IR10 $ high_ad_IR11;
xxh3 = high_ad_IR12 $ high_ad_IR13 $ high_ad_IR14 $ high_ad_IR15;
xxh4 = high_ad_IR16 $ high_ad_IR17 $ high_ad_IR18 $ high_ad_IR19;
xxh5 = high_ad_IR20 $ high_ad_IR21 $ high_ad_IR22 $ high_ad_IR23;
xxh6 = high_ad_IR24 $ high_ad_IR25 $ high_ad_IR26 $ high_ad_IR27;
xxh7 = high_ad_IR28 $ high_ad_IR29 $ high_ad_IR30 $ high_ad_IR31;
xxh8 = high_cbeN_IR0 $ high_cbeN_IR1 $ high_cbeN_IR2 $ high_cbeN_IR3;
xxh9 = xxh0 $ xxh1 $ xxh2 $ xxh3;
xxh10 = xxh4 $ xxh5 $ xxh6 $ xxh7;
xxh11 = xxh8 $ xxh9 $ xxh10;
xor_chk_out64 = xxh11 ;
--
-- par error is detectd when output of xor tree and par are different
--
-- You can avoid the CASCADE chain by replicating the logic and doing the AND gate implementation
-- before the XOR ie with the output of xor_36. This is wherever par_error is used.
--
--JOT par_error_stat = xor_chk_out xor par xor xor_chk_out64 xor par64; -- Par and xor tree output are differen
--JOT par_error_perr = xor_chk_out xor par xor xor_chk_out64 xor par64; -- Par and xor tree output are differen
--JOT par_error_serr = xor_chk_out xor par xor xor_chk_out64 xor par64; -- Par and xor tree output are differen
par_error = (xor_chk_out xor par);-- and (not trg_adr_phase_out); --and lm_adr_ackn);
par_error64 = (xor_chk_out64 xor par64);
-- par_error_stat = (par_error or par_error64);-- and (not trg_adr_phase_out);-- and lm_adr_ackn); -- Par and xor tree output are differen
-- par_error_perr = (par_error or par_error64);-- and (not trg_adr_phase_out);-- and lm_adr_ackn); -- Par and xor tree output are differen
par_error_serr = (xor_chk_outad xor par);-- and (trg_adr_phase_out);-- or not lm_adr_ackn); -- or (xor_chk_out64 xor par64); -- Par and xor tree output are differen
-- Parity error Output is set when either master or target detected a parity error
-- and parity error reporting is enabled in the Config Command Register.
--
perr_OR_not.clk = clk;
-- perr_OR.clrn = rstn;
perr_OR_not.prn = rstn;
-- perr_OR = (par_error and (mstr_perr_vld or targ_perr_vld) and perr_ena)
-- OR (par_error64 and ((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out)) and perr_ena);
-- perr_OR = (par_error and (mstr_perr_vld or targ_perr_vld) and perr_ena)
-- OR (par_error64 and perr_ena and (mstr_perr_vld and mstr_64_trans_out) )
-- OR (par_error64 and perr_ena and (targ_perr_vld and trg_64_trans_out) );
perr_OR_not_lc1 = LCELL( (mstr_perr_vld or targ_perr_vld) and perr_ena);
perr_OR_not_lc2 = LCELL(perr_ena and mstr_perr_vld and mstr_64_trans_out );
perr_OR_not_lc3 = LCELL(perr_ena and targ_perr_vld and trg_64_trans_out);
perr_OR_not = not ( (par_error and perr_OR_not_lc1 ) )
and CASCADE ( not (par_error64 and ( perr_OR_not_lc2
OR
perr_OR_not_lc3)
)
);
-- perr_OR_not = not ( (par_error and (mstr_perr_vld or targ_perr_vld) and perr_ena) )
-- AND CASCADE ( (not( (par_error64 and perr_ena and mstr_perr_vld and mstr_64_trans_out )))
-- AND CASCADE ( not( (par_error64 and perr_ena and targ_perr_vld and trg_64_trans_out)))
-- );
perr_OR = not perr_OR_not;
perr_out = perr_OR;
--
-- System error is asserted if a target address phase detected a parity error and
-- both perr reporting and serr reporting are set
--
serr_OR.clk = clk;
serr_OR.clrn = rstn;
-- serr_OR = LCELL (targ_serr_vld and serr_ena and perr_ena) and par_error_serr;
serr_or_lc = LCELL(targ_serr_vld and serr_ena and perr_ena);
serr_OR = serr_or_lc and par_error_serr;
serr_out = serr_OR;
--
-- serr_sig_set: This is set whenever the target asserts serr.
--
serr_sig_set = serr_OR;
--
-- perr_det_setR is a register to remove par from the path.
-- perr det bit in status regsiter must be set when a parity error is detected even
-- if the parity error reporting is not enabled in the command register
--
---------- CASCADE OPTIMIZATION -------------------------------------------------------------
%
perr_det_setR_not.clk = clk;
-- perr_det_setR.clrn = rstn;
perr_det_setR_not.prn = rstn;
-- perr_det_setR = (mstr_perr_vld OR targ_perr_vld OR targ_serr_vld) and par_error;
-- perr_det_setR = ((((trg_64_trans_out and targ_perr_vld) or (mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and par_error_stat)
-- OR
-- ((((not trg_64_trans_out and targ_perr_vld) or (not mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and (par_error or par_error_serr))
-- ;
-- perr_det_setR = (par_error and (mstr_perr_vld or targ_perr_vld))
-- OR (par_error64 and ((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out)))
-- OR (targ_serr_vld and par_error_serr);
perr_det_setR_not = not (par_error64 and LCELL ( (mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out) ) )
and CASCADE ( (not (par_error and (mstr_perr_vld or targ_perr_vld) ) )
and CASCADE ( not (targ_serr_vld and par_error_serr) )
);
perr_det_setR = not perr_det_setR_not;
perr_det_set = perr_det_setR;
%
------------------------------------------------------------------------------------------------
-------------- REGISTER-OR OPTIMIZATION -----------------------------------------------------
-- perr_det_setR.clk = clk;
-- perr_det_setR.clrn = rstn;
-- perr_det_setR_not.prn = rstn;
-- perr_det_setR = (mstr_perr_vld OR targ_perr_vld OR targ_serr_vld) and par_error;
-- perr_det_setR = ((((trg_64_trans_out and targ_perr_vld) or (mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and par_error_stat)
-- OR
-- ((((not trg_64_trans_out and targ_perr_vld) or (not mstr_64_trans_out and mstr_perr_vld) or targ_serr_vld)) and (par_error or par_error_serr))
-- ;
-- perr_det_setR = (par_error and (mstr_perr_vld or targ_perr_vld))
-- OR (par_error64 and ((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out)))
-- OR (targ_serr_vld and par_error_serr);
-- perr_det_setR_not = not (par_error64 and LCELL ( (mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out) ) )
-- and CASCADE ( (not (par_error and (mstr_perr_vld or targ_perr_vld) ) )
-- and CASCADE ( not (targ_serr_vld and par_error_serr) )
-- );
perr_det_setR_r1.clk = clk;
perr_det_setR_r1.clrn = rstn;
perr_det_setR_r1_d = (par_error and (mstr_perr_vld or targ_perr_vld));
perr_det_setR_r1.d = perr_det_setR_r1_d;
perr_det_setR_r2.clk = clk;
perr_det_setR_r2.clrn = rstn;
perr_det_setR_r2_d = (par_error64 and LCELL((mstr_perr_vld and mstr_64_trans_out) or (targ_perr_vld and trg_64_trans_out)));
perr_det_setR_r2.d = perr_det_setR_r2_d;
perr_det_setR_r3.clk = clk;
perr_det_setR_r3.clrn = rstn;
perr_det_setR_r3_d = (targ_serr_vld and par_error_serr);
perr_det_setR_r3.d = perr_det_setR_r3_d;
perr_det_setR = perr_det_setR_r1 or perr_det_setR_r2 or perr_det_setR_r3;
perr_det_set = perr_det_setR;
% Ziad's optimization
--
-- Parity error Output is set when either master or target detected a parity error
-- and parity error reporting is enabled in the Config Command Register.
--
perr_OR.clk = clk;
perr_OR.clrn = rstn;
perr_OR = cascade ( (mstr_perr_vld or targ_perr_vld) and perr_ena) and par_error_perr;
perr_out = perr_OR;
--
-- System error is asserted if a target address phase detected a parity error and
-- both perr reporting and serr reporting are set
--
serr_OR.clk = clk;
serr_OR.clrn = rstn;
serr_OR = cascade (targ_serr_vld and serr_ena and perr_ena) and (par_error_serr);
serr_out = serr_OR;
--
-- serr_sig_set: This is set whenever the target asserts serr.
--
serr_sig_set = serr_OR;
--
-- perr_det_setR is a register to remove par from the path.
-- perr det bit in status regsiter must be set when a parity error is detected even
-- if the parity error reporting is not enabled in the command register
--
perr_det_setR.clk = clk;
perr_det_setR.clrn = rstn;
perr_det_setR = cascade (mstr_perr_vld OR targ_perr_vld OR targ_serr_vld) and par_error_stat;
perr_det_set = perr_det_setR;
%
END;
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