📄 pcic_c.tdf
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-- WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
-- This is an automatically generated file. Do not, under any circumstances modify this file!!!!
-- File Name: config.tdf
-- Function : This control the Configuration Access of the PCI/B MegaCore
-- Author : Ziad M. Abu-Lebdeh
-- Rev History
-- 5/97 Initial Entry
--
-- $History: pcic_c.tdf $
--
-- ***************** Version 63 *****************
-- User: Otan Date: 6/16/99 Time: 5:55p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 62 *****************
-- User: Otan Date: 6/16/99 Time: 4:27p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 58 *****************
-- User: Otan Date: 6/14/99 Time: 6:41p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 57 *****************
-- User: Otan Date: 6/14/99 Time: 1:15p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Optimized frame_or and req64_or for setup
--
-- ***************** Version 56 *****************
-- User: Otan Date: 6/12/99 Time: 3:40p
-- Updated in $/MegaCore/HandOff/45/source/src
-- optimized adr_phase
--
-- ***************** Version 55 *****************
-- User: Otan Date: 6/11/99 Time: 11:36a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 54 *****************
-- User: Otan Date: 6/11/99 Time: 11:26a
-- Updated in $/MegaCore/HandOff/45/source/src
-- More optimization. targ_oer, high_ad_or, bar_hit[5..0]
--
-- ***************** Version 53 *****************
-- User: Otan Date: 6/09/99 Time: 9:19a
-- Updated in $/MegaCore/HandOff/45/source/src
-- all features added - only 8 LSB of BAR1 are read/write in a 64-bit BAR
--
-- ***************** Version 43 *****************
-- User: Ziada Date: 3/15/99 Time: 5:41p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added New parameter PCI_66MHZ_CAPABLE, And added bits 4, 5 to the
-- Status register
--
-- ***************** Version 19 *****************
-- User: Ziada Date: 3/15/99 Time: 9:59a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Updated to add support for MRL and MRM and MWI to expansion ROM BAR
--
-- ***************** Version 18 *****************
-- User: Ziada Date: 3/14/99 Time: 1:23p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Corrected Problem with using 2Gig for BAR and Set default values for
-- config module
--
-- ***************** Version 54 *****************
-- User: Otan Date: 3/14/99 Time: 8:59a
-- Updated in $/MegaCore/HandOff/45/source/src
-- pre1.0-2
--
-- ***************** Version 53 *****************
-- User: Otan Date: 3/04/99 Time: 4:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Updated the configuration files, similar to pci_b
--
-- ***************** Version 17 *****************
-- User: Ziada Date: 2/09/99 Time: 8:52p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Corrected Problem With Bar Hit being enabled when no legitimate cycle
-- is available
--
-- ***************** Version 16 *****************
-- User: Ziada Date: 2/03/99 Time: 3:22p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Corrected Problem with bar_hitR.rst not being decalared
--
-- ***************** Version 15 *****************
-- User: Ziada Date: 1/22/99 Time: 12:07p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Updated files for Joseph Impastata
--
-- ***************** Version 14 *****************
-- User: Ziada Date: 1/22/99 Time: 10:30a
-- Updated in $/MegaCore/HandOff/35/source/src
-- Changed Default Value for EXP ROM Parameters
--
-- ***************** Version 13 *****************
-- User: Ziada Date: 1/08/99 Time: 5:00p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added Expansion ROM BAR
-- Changed CAP_PTR_ENA to be Text Value insted of Decimal
--
-- ***************** Version 12 *****************
-- User: Otan Date: 10/13/98 Time: 2:19p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added CompactPCI Hot Swap Capability. Added CAP_LIST_ENA and CAP_PTR
-- parameters.
--
-- ***************** Version 11 *****************
-- User: Ziada Date: 9/20/98 Time: 5:34p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added support for MRL MWI and MRM
--
-- ***************** Version 10 *****************
-- User: Ziada Date: 9/11/98 Time: 6:29p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Removed unnecessary comments
-- Added CORE Parameter
-- Added Logic necessary for Target Only Section
--
-- ***************** Version 9 *****************
-- User: Ziada Date: 9/09/98 Time: 6:11p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Changed File Names for Release
--
-- ***************** Version 8 *****************
-- User: Ziada Date: 9/09/98 Time: 5:57p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Corrected Problem with I/O BAR having 16 Bytes allocated.
-- Synchronized config_in with config moduel
--
-- ***************** Version 7 *****************
-- User: Ziada Date: 5/28/98 Time: 6:36p
-- Updated in $/MegaCore/HandOff/35/source/src
-- changed Name of parameter L_HOST_INTERFACE_ENA to HOST_INTERFACE_ENA
--
-- ***************** Version 6 *****************
-- User: Brians Date: 4/27/98 Time: 12:42p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Optimized for 10K30A-1
--
-- ***************** Version 5 *****************
-- User: Ziada Date: 3/23/98 Time: 6:57p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Added Support for Local Side Host to write Configuration space
--
-- ***************** Version 4 *****************
-- User: Ziada Date: 3/19/98 Time: 7:04p
-- Updated in $/MegaCore/HandOff/35/source/src
-- Updated to make both config_in and config.tdf run together after a
-- disconnect from 11/11/97 till 19/3/1998.
--
-- **************************************************************
-- Here is the updates for the time from 11/11/97 till 3/19/1998
-- I got this from comments in config.tdf
--
-- corrected interrupt Pin register value to 1 istead of 0
-- Updated default values for parameters
-- Code First cut.
-- corrected warnings from junk
-- Removed Extra Signals
-- Added Junk to removed unused signal Warnings
-- Removed Cache line register, Latency Timer Counter.
-- Changed logic for Parity error reporting status registers to minimize
-- critical times on par
-- *********************************************************************
-- ***************** Version 2 *****************
-- User: Ziada Date: 11/11/97 Time: 3:57p
-- Updated in $/MegaCore/HandOff/40/source/src
-- Updated Parameter Declaration and Message Generation for Size of Memory
-- Reserved
--
-- ***************** Version 12 *****************
-- User: Ziada Date: 10/01/97 Time: 2:51p
-- Updated in $/MegaCore/HandOff/40/source/src
-- * Corrected The Typo with using BAR0_PREFETCH in info messages for
-- other BARs
-- * Changed Command Register Bit 2 from R/W to Read Only (Master
-- Enable)
--
-- ***************** Version 10 *****************
-- User: Ziada Date: 9/23/97 Time: 11:35a
-- Updated in $/MegaCore/HandOff/40/src
-- Added History Statement to Header
--
--
-- Function prototype for pcic_cd: pci_b configuration space decoder
FUNCTION pcic_cd (clk, rstn, ena, dat[5..0])
RETURNS (dec0r, dec1r, dec2r, dec3r, dec4r, dec5r, dec6r, dec7r, dec8r, dec9r, dec11r, dec12r, dec13r, dec15r);
-- Function prototype for pcic_sr: pci_b set/reset flip flop with set dominant
FUNCTION pcic_sr(s, r, clk, clrn, prn)
RETURNS (q);
INCLUDE "maxplus2.inc";
PARAMETERS
(
CAP_LIST_ENA = "NO", -- Capabilities List
CAP_PTR = H"40",
EXP_ROM_ENA = "NO",
PCI_66MHZ_CAPABLE = "YES",
EXP_ROM_BAR = H"FF000000", -- EXpansion ROM Base Address Register
USE_EXP_ROM_DEFAULT = "NO", -- Use The Expansion ROM BAR
EXP_ROM_DEFAULT = H"FF000000", -- Expansion ROM Power Up Value
CORE = "MASTER", -- Type of Interface
LOCAL_CONFIG_ENA = "NO", -- Local Configuration Enable
HOST_BRIDGE_ENA = "NO", -- Enable Host Bridge Support
VENDOR_ID = H"1172", -- Vendor ID Register
DEVICE_ID = H"0002", -- Device ID Register
REVISION_ID = H"01", -- Revision ID Register
CLASS_CODE = H"FF0000", -- Class Code Register
SUBSYSTEM_ID = H"FF00", -- Subsystem ID Register
SUBSYSTEM_VENDOR_ID = H"FF00", -- Subsystem Vendor ID Register
MIN_GRANT = H"00", -- Minimum Grant Register
MAX_LATENCY = H"00", -- Maximum Latency Register
-- Values in BAR0
-- Bit(0) = 0-Memory, 1-I/O Space
-- Bit(1) = Reserve for I/O Space
-- Bit(2,1) = Memory Type
-- Bit(3) = Prefetchable Memory Address
-- Bits(31..n) = 1 for number of decode bits
BAR0 = H"00000004" ,
BAR1 = H"FFFFFF00" ,
BAR2 = H"F0000000" ,
BAR3 = H"F0000000" ,
BAR4 = H"F0000000" ,
BAR5 = H"F0000000" ,
NUMBER_OF_BARS -- Number of Base Address Regisers to be used
);
define bar_rob(bar_ovfl_n, bar) = (bar_ovfl_n > 0 ) ? CEIL(LOG2(0-(bar & H"FFFFFFF0"))) : 31 ;
define bar_rob_64(bar_ovfl_n, bar, bar, bar) = (bar_ovfl_n > 0 OR (bar!=H"00000004" and bar!=H"0000000C")) ? CEIL(LOG2(0-(bar & H"FFFFFFFF"))) : 32 ; -- if BAR1 = H"FFFFFFFF" or BAR0 = H"00000004(C)"
--define bar_rw_64(bar_ovfl_n, bar, bar, bar) = (bar_ovfl_n > 0 OR (bar!=H"00000004" and bar!=H"0000000C")) ? CEIL(LOG2(0-(bar & H"000000FF"))) : 32 ; -- only least 8 signicant bits can be read/write
define bar_rw_64(bar_mem_loc, bar_read_only) = (bar_mem_loc == 2) ? (8-bar_read_only) : 0;
-- calculate the number of Bits in BAR to be read only.
constant EXP_ROM_READ_ONLY_BITS = CEIL(LOG2(0-(EXP_ROM_BAR & H"FFFFF800")));
constant BAR0_OVFL_N = (BAR0 & H"7FFFFFF0"); -- 1: Not over flow, 0: over flow
constant BAR0_READ_ONLY_BITS = bar_rob(BAR0_OVFL_N, BAR0);
constant BAR0_READ_ONLY_BITS_32 = bar_rob_64(BAR0_OVFL_N, BAR0, BAR0, BAR0);
constant BAR0_LS_NIBBLE = (BAR0 & H"0000000F");
constant BAR0_TYPE = (BAR0 & H"00000001");
constant BAR0_MEM_LOC = (BAR0 & H"00000006") DIV 2;
constant BAR0_PREFETCH = (BAR0 & H"00000008") DIV 8;
constant BAR1_OVFL_N = (BAR1 & H"7FFFFFF0"); -- 1: Not over flow, 0: over flow
constant BAR1_ALL_0 = H"00";
constant BAR1_READ_ONLY_BITS = bar_rob(BAR1_OVFL_N, BAR1);
constant BAR1_READ_ONLY_BITS_0 = (bar_rob_64(BAR1_OVFL_N, BAR1, BAR1, BAR1));
constant BAR1_READ_WRITE_BITS = bar_rw_64(BAR0_MEM_LOC, BAR1_READ_ONLY_BITS_0);
constant BAR1_LS_NIBBLE = (BAR1 & H"0000000F");
constant BAR1_TYPE = (BAR1 & H"00000001");
constant BAR1_MEM_LOC = (BAR1 & H"00000006") DIV 2;
constant BAR1_PREFETCH = (BAR1 & H"00000008") DIV 8;
constant BAR2_OVFL_N = (BAR2 & H"7FFFFFF0"); -- 1: Not over flow, 0: over flow
constant BAR2_READ_ONLY_BITS = bar_rob(BAR2_OVFL_N, BAR2);
constant BAR2_LS_NIBBLE = (BAR2 & H"0000000F");
constant BAR2_TYPE = (BAR2 & H"00000001");
constant BAR2_MEM_LOC = (BAR2 & H"00000006") DIV 2;
constant BAR2_PREFETCH = (BAR2 & H"00000008") DIV 8;
constant BAR3_OVFL_N = (BAR3 & H"7FFFFFF0"); -- 1: Not over flow, 0: over flow
constant BAR3_READ_ONLY_BITS = bar_rob(BAR3_OVFL_N, BAR3);
constant BAR3_LS_NIBBLE = (BAR3 & H"0000000F");
constant BAR3_TYPE = (BAR3 & H"00000001");
constant BAR3_MEM_LOC = (BAR3 & H"00000006") DIV 2;
constant BAR3_PREFETCH = (BAR3 & H"00000008") DIV 8;
constant BAR4_OVFL_N = (BAR4 & H"7FFFFFF0"); -- 1: Not over flow, 0: over flow
constant BAR4_READ_ONLY_BITS = bar_rob(BAR4_OVFL_N, BAR4);
constant BAR4_LS_NIBBLE = (BAR4 & H"0000000F");
constant BAR4_TYPE = (BAR4 & H"00000001");
constant BAR4_MEM_LOC = (BAR4 & H"00000006") DIV 2;
constant BAR4_PREFETCH = (BAR4 & H"00000008") DIV 8;
constant BAR5_OVFL_N = (BAR5 & H"7FFFFFF0"); -- 1: Not over flow, 0: over flow
constant BAR5_READ_ONLY_BITS = bar_rob(BAR5_OVFL_N, BAR5);
constant BAR5_LS_NIBBLE = (BAR5 & H"0000000F");
constant BAR5_TYPE = (BAR5 & H"00000001");
constant BAR5_MEM_LOC = (BAR5 & H"00000006") DIV 2;
constant BAR5_PREFETCH = (BAR5 & H"00000008") DIV 8;
constant BAR_64BIT_ROB_BAR0 = BAR0_READ_ONLY_BITS + BAR1_READ_ONLY_BITS_0; -- IF BAR1=H"FFFFFFFF" and BAR0=H"XXXXXXX4(C)"
constant BAR_64BIT_ROB_BAR01 = BAR0_READ_ONLY_BITS_32 + BAR1_READ_ONLY_BITS; -- IF BAR1=H"XXXXXXXX" and BAR0=H"00000004(C)"
SUBDESIGN 'pcic_c'
(
-- PCI Input Signals
clk : INPUT; -- PCI Clock
rstn : INPUT; -- PCI Reset
cben_IR[3..0] : INPUT; -- Registered cben signals
ad_IR[31..0] : INPUT; -- Registered PCI Address/Data Bus
ad_ir_addr[31..0] : INPUT;
cben_ir_addr[3..0] : INPUT;
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