📄 pci_c.tdf
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l_ldat_ack : NODE;
l_hdat_ack : NODE;
local_dat_sel : LCELL;--NODE;
lt_sel_w : NODE;
--jot mstr_hr_adr_sel : node;
mstr_64_trans_out : node;
mstr_ad_ir_ce_a : node;
mstr_cben_ir_ce_a : node;
mstr_cben_ir_ce_d : LCELL;--NODE;
-- 64bit_PCI : node;
-- Local Side Configuration Space Support
lcfg_adr[7..0] : NODE; -- Local Configuration Address
lcfg_ben[3..0] : NODE; -- Local Configuration Byte enables
lcfg_dati[31..0] : NODE; -- Local Configuration Data Input Bus
lcfg_adr_vld : NODE; -- Local Configuration Address Valid
lcfg_dat_vld : NODE; -- Local Configuration data Valid
lcfg_dato[31..0] : NODE; -- Local Configuration Data Output
-- trg_dac_sr : NODE;
BEGIN
lcfg_adr[7..0] = GND; -- Local Configuration Address
lcfg_ben[3..0] = GND; -- Local Configuration Byte enables
lcfg_dati[31..0] = GND; -- Local Configuration Data Input Bus
lcfg_adr_vld = GND; -- Local Configuration Address Valid
lcfg_dat_vld = GND; -- Local Configuration data Valid
lcfg_dato[31..0] = lcfg_dato[31..0]; -- Local Configuration Data Output
ASSERT REPORT "Compiling Altera's pci_c MegaCore. % " REVISION
SEVERITY INFO;
--
-- Instantiate Parity Checker par_chk.tdf
--
parity_chk.clk = clk; -- PCI clk Input
parity_chk.rstn = rstn; -- PCI rstn Input
parity_chk.par = par; -- PCI par signal
parity_chk.par64 = par64; -- PCI par64 signal
--JOT parity_chk.low_ad_IR[31..0] = (low_ad_IR_data[31..0] & ad_IR_ce_data)
--JOT # (ad_IR_address[31..0] & ad_IR_ce_address);-- PCI AD Bus Input Registers
--JOT parity_chk.low_cben_IR[3..0]= (low_cben_IR_data[3..0] & cben_IR_ce_data)
--JOT # (cben_IR_address[3..0] & cben_IR_ce_address);-- PCI CBE Bus Input Registers -- PCI CBEN Bus Input Registers
parity_chk.trg_64_trans_out = trg_64_trans_out;
parity_chk.mstr_64_trans_out = mstr_64_trans_out;
--jot parity_chk.trg_adr_phase_out = trg_adr_phase_out;
--jot parity_chk.lm_adr_ackn = lm_adr_ackn;
parity_chk.low_ad_IR_addr[31..0] = (ad_IR_address[31..0]);-- & parity_ad_ir_ce_address);-- PCI AD Bus Input Registers
parity_chk.low_cben_IR_addr[3..0] = (cben_IR_address[3..0]);-- & parity_cben_ir_ce_address);-- PCI CBE Bus Input Registers -- PCI CBEN Bus Input Registers
-- parity_ad_ir_ce_address = (ad_IR_ce_address or trg_adr_phase_out);
-- parity_cben_ir_ce_address = (cben_IR_ce_address or trg_adr_phase_out);
parity_chk.low_ad_IR[31..0] = (low_ad_IR_data[31..0] %& ad_IR_ce_data%); -- PCI AD Bus Input Registers
parity_chk.low_cben_IR[3..0] = (low_cben_IR_data[3..0] %& cben_IR_ce_data%); -- PCI CBEN Bus Input Registers
parity_chk.high_ad_IR[31..0] = (high_ad_IR_data[31..0]);-- and not trg_cfg_cyc_out %& ad_IR_ce_data%); -- PCI AD Bus Input Registers
parity_chk.high_cben_IR[3..0] = (high_cben_IR_data[3..0] %& cben_IR_ce_data%); -- PCI CBE Bus Input Registers -- PCI CBEN Bus Input Registers
parity_chk.perr_ena = perr_ena; -- Configuration Command Register Parity Enable
parity_chk.serr_ena = serr_ena; -- Configuration Command Register System Error Enable
parity_chk.mstr_perr_vld = mstr_perr_vld; -- Master Data Parity error valid
parity_chk.targ_perr_vld = trg_perr_vld; -- Target Data Parity error Valid
parity_chk.targ_serr_vld = trg_serr_vld; -- Target System Error valid
perr_det_set = parity_chk.perr_det_set; -- PERR Detect Set, Config Status Register Bit 15 Set
serr_sig_set = parity_chk.serr_sig_set; -- System Error Signaled Set
perr_out = parity_chk.perr_out; -- Parity Error Output
serr_out = parity_chk.serr_out; -- System Error Output
-- ************************************************************************
-- **** Instantiate the pcic_pg.tdf ****
-- ************************************************************************
parity_gen.data[31..0] = low_ad_OR[31..0]; -- Data Input
parity_gen.cbeN[3..0] = cben[3..0]; -- Command/Byte Enable
--JOT parity_gen.cbeN[3..0] = low_cben_or[3..0]; -- Command/Byte Enable
par_gen_out = parity_gen.parity; -- Parity Output
parity_gen64.data[31..0] = high_ad_OR[63..32]; -- Data Input
parity_gen64.cbeN[3..0] = cben[7..4]; -- Command/Byte Enable
par_gen_out64 = parity_gen64.parity; -- Parity Output
-- Parity Checking Logic
-- pchk_ena = cfg_pchk_ena; -- This will tell if parity_chk output is valid
-- pchk_error = par xor par_chk_out; -- Check if parity Input matches Parity Expected
-- Set PERRN (Driven During Master Reads and Target Writes)
--
-- Instantiate the target Module
--
-- PCI Signal Inputs
trg.clk = clk; -- PCI Clock
trg.rstn = rstn; -- PCI Reset
trg.ad_IR_address[31..0] = ad_IR_address[31..0]; -- AD Input Registers
trg.ad_ir_data[31..0] = low_ad_ir_data[31..0];
trg.cben_IR_address[3..0] = cben_IR_address[3..0]; -- Command/Byte Enable Input Registers
trg.cben_ir_data[3..0] = low_cben_ir_data[3..0];
trg.frame = frame; -- Active High FRAMEn Input
trg.irdy = irdy; -- Active High IRDYn Input
trg.idsel = idsel; -- IDSEL Input Register
trg.req64 = req64;
-- Local Side Inputs
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
trg.low_lt_dati[31..0] = l_dati[31..0]; -- Local Target Data Input
trg.high_lt_dati[31..0] = l_dati[63..32]; -- Local Target Data Input
ELSE GENERATE
trg.low_lt_dati[31..0] = l_adi[31..0]; -- Local Target Data Input
trg.high_lt_dati[31..0] = l_adi[63..32]; -- Local Target Data Input
END GENERATE;
trg.lt_rdyn = lt_rdyn; -- Local Target Ready Input
trg.lt_discn = lt_discn; -- Local Target Disconnect Input
trg.lt_abortn = lt_abortn; -- Local Target Abort Input
-- trg.64bit_PCI = 64bit_PCI ; -- Indicates a pure 64bit system
-- Input from Parity Checker
-- trg.pchk_error = pchk_error; -- Parity Checker Not same as PAR detected
trg.perr_rep_set = perr_rep_set; -- Data Parity Error Signaled
trg.perr_det_set = perr_det_set; -- Parity Error Detected
trg.serr_sig_set = serr_sig_set; -- System Parity Error Signaled
trg.mstr_dac_decode = mstr_dac_decode;
trg.mstr_actv = mstr_actv; -- Master is Active. Has PCI Bus
trg.mstr_abrt_set = mstr_abrt_set; -- Master Abort Set
trg.targ_abrt_set = targ_abrt_set; -- Target Abort Set
trg.lm_ackn = lm_ackn;
trg_serr_vld = trg.serr_vld; -- SERR Valid
trg_perr_vld = trg.perr_vld; -- Parity Error was detected
trg_perr_oe = trg.perr_oe; -- PERR Output Enable
trg_par_oe = trg.par_oe; -- PAR Output Enable
-- Local Side Outputs
l_adro[63..0] = trg.lt_adr[63..0]; -- Local Target Address
l_cmdo[3..0] = trg.lt_cmd[3..0]; -- Local Target Command
lt_ldata_ackn = trg.lt_ldata_ackn;
lt_hdata_ackn = trg.lt_hdata_ackn;
lt_sel_w = trg.lt_sel_w;
-- lt_lackn = trg.lt_lackn; -- Target Low Data Acknowledge
-- lt_hackn = trg.lt_hackn; -- Target High Data Acknowledge
lt_tsr[11..0] = trg.lt_tsr[11..0]; -- Local Target Transaction Status Registers
lt_dxfrn = trg.lt_dxfrn; -- Local Target Data Transfer
lt_framen = trg.lt_framen; -- Local Target Frame
lt_ackn = trg.lt_ackn; -- Local target Acknowledge
-- AD Bus Controls
-- trg_ad_ce = trg.ad_ce; -- Target AD Output Registers clock Enable
trg_ad_oe = trg.ad_oe; -- Target AD OE Output
trg_ad_sel = trg.ad_sel; -- AD Output Mux Select
-- trg_dac_sr = trg.dac_sr_out;
trg_ad_IR_ce_D = trg.ad_IR_ce_D; -- Target Address Clock Enable
trg_ad_IR_ce_A = trg.ad_IR_ce_A; -- Target Data Clock Enable
trg_cben_IR_ce_D = trg.cben_IR_ce_D; -- Target Address Clock Enable
trg_cben_IR_ce_A = trg.cben_IR_ce_A; -- Target Data Clock Enable
trg_low_data_out[31..0] = trg.low_data_out[31..0];
trg_high_data_out[31..0] = trg.high_data_out[31..0];
trg_cfg_dat_out[31..0] = trg.cfg_dat_out[31..0]; -- Configuration data Output to AD Output Register
trg_cfg_cyc_out = trg.cfg_cyc_out; -- Configuratiob Cycle Indicator
trg_hr_dat_sel = trg.hr_dat_sel; -- Holding Register Select Signal
trg_dati_HR_ena = trg.dati_HR_ena; -- Holding Register Enable Signal
hi_low_sel = trg.hi_low_sel;
trg_64_trans_out = trg.64_trans_out;
-- trg_adr_phase_out = trg.adr_phase_out;
-- Target Control Signal Outputs
targ_oeR = trg.targ_oeR; -- Output Enable Signal for Target Controls
trdy_out = trg.trdy_out; -- PCI Target Ready Output
devsel_out = trg.devsel_out; -- PCI Device Select Output
stop_out = trg.stop_out; -- PCI Stop Output
ack64_out = trg.ack64_out;
-- Local Command Register Outputs
io_ena = trg.io_ena; -- I/O Space Enable
mem_ena = trg.mem_ena; -- Memory Space Enable
mstr_ena = trg.mstr_ena; -- Bus Master Enable
mwi_ena = trg.mwi_ena; -- Memory Write and Invalidate Enable
perr_ena = trg.perr_ena; -- Pariy Error Response Enable
serr_ena = trg.serr_ena; -- SERR Enable
-- Local Status Register Outputs
perr_rep = trg.cfg_perr_rep; -- Data Parity Error Signaled
tabort_sig = trg.cfg_tabrt_sig; -- Signaled Target Abort
tabort_rcvd = trg.cfg_tabrt_rcvd; -- Recieved Target Abort
mabort_rcvd = trg.cfg_mabrt_rcvd; -- Recieved Master Abort
serr_sig = trg.cfg_serr_sig; -- Signaled SERR
perr_det = trg.cfg_perr_det; -- Detected Parity Error
-- Other Local Configuration Register Outputs
lat_dat[7..0] = trg.lat_dat[7..0]; -- Latency Timer Register Data
cache[7..0] = trg.cache_dat[7..0]; -- Cache Line Register Data
-- bar_hit[5..0] = trg.base_hit[5..0]; -- Base Address Register Comparison Outputs
-- Local Side Configuration Space Support
trg.lcfg_adr[7..0] = lcfg_adr[7..0]; -- Local Configuration Address
trg.lcfg_ben[3..0] = lcfg_ben[3..0]; -- Local Configuration Byte enables
trg.lcfg_dat_in[31..0] = lcfg_dati[31..0]; -- Local Configuration Data Input Bus
trg.lcfg_adr_vld = lcfg_adr_vld; -- Local Configuration Address Valid
trg.lcfg_dat_vld = lcfg_dat_vld; -- Local Configuration data Valid
lcfg_dato[31..0] = trg.lcfg_dat_out[31..0];-- Local Configuration Data Output
-- AD_CE addition
trg_ADOR_ena = trg.ADOR_ena;
ador_hi_dena = trg.ador_hi_dena;
m_ador_hi_dena = mstr.ador_hi_dena;
mstr_hi_low_sel = mstr.hi_low_sel;
-- ***************************************************************************
-- ************************************************************************
-- **** Instantiate pcic_m.tdf ****
-- ************************************************************************
-- PCI Inputs
mstr.clk = clk; -- PCI Clock
mstr.rstn = rstn; -- PCI Restet
mstr.gnt = gnt; -- Active High PCI Grant Signal
mstr.frame = frame; -- Active High FRAMEn Input
mstr.irdy = irdy; -- Active High IRDYn INPUT
mstr.trdy = trdy; -- Active High TRDYn Input
mstr.devsel = devsel; -- Active High DEVSELn Input
mstr.stop = stop; -- Active High STOPn Input
mstr.ack64 = ack64;
mstr.perr = perr; -- Active high
-- Configuration Space Inputs
mstr.mstr_ena = mstr_ena ; -- Master Enable
mstr.lat_dat[7..0] = lat_dat[7..0] ; -- Latency Timer Register Data
-- Local Side Inputs
mstr.lm_req64 = lm_req64 ; -- Local Side Master Access Request Signal
mstr.lm_req32 = lm_req32 ; -- Local Side Master Access Request Signal
-- mstr.lm_adr64 = lm_adr64 ; -- Local Side Master 64-bit Address Request Signal
mstr.lm_last = lm_last ; -- Local Side Master Access Request Signal
mstr.lm_rdyn = lm_rdyn ; -- Local Side Master Data Ready Input
IF (DUAL_ADDRESS_ENA == "NO") GENERATE
mstr.low_lm_dati[31..0] = l_dati[31..0] ; -- Local Side Master Address/Data Bus
mstr.high_lm_dati[31..0]= l_dati[63..32]; -- Local Side Master Address/Data Bus
mstr.low_lm_beni[3..0] = l_beni[3..0] ; -- Local Side Master Command/Byte Enables
mstr.high_lm_beni[3..0] = l_beni[7..4] ; -- Local Side Master Command/Byte Enables
mstr.lm_adri[31..0] = l_adri[31..0] ; -- Local Side Master Address/Data Bus
mstr.lm_cmd[3..0] = l_cmdi[3..0] ; -- Local Side Command Signal
ELSE GENERATE
mstr.low_lm_dati[31..0] = l_adi[31..0] ; -- Local Side Master Address/Data Bus
mstr.high_lm_dati[31..0]= l_adi[63..32]; -- Local Side Master Address/Data Bus
mstr.low_lm_beni[3..0] = l_cbeni[3..0] ; -- Local Side Master Command/Byte Enables
mstr.high_lm_beni[3..0] = l_cbeni[7..4] ; -- Local Side Master Command/Byte Enables
-- mstr.lm_adri[31..0] = l_adi[31..0] ; -- Local Side Master Address/Data Bus
-- mstr.lm_cmd[3..0] = l_cbeni[3..0] ; -- Local Side Command Signal
END GENERATE;
-- mstr.64bit_PCI = 64bit_PCI ; -- Indicates a pure 64bit system
-- PCI Outputs
-- AD Bus Controls
mstr_low_data_out[31..0] = mstr.low_data_out[31..0]; -- Master Output Data to AD Output Register
mstr_high_data_out[31..0] = mstr.high_data_out[31..0];-- Master Output Data to AD Output Register
mstr_ad_oe = mstr.ad_oe ; -- Master AD OE Output
mstr_ad_sel = mstr.ad_sel ; -- Master AD Output Mux Select
mstr_ad_IR_ce_D = mstr.ad_IR_ce_D ; -- AD Input Register Clock Enable
mstr_hr_dat_sel = mstr.hr_dat_sel ;
mstr_dati_HR_ena = mstr.dati_HR_ena ;
mstr_ADOR_ena = mstr.ADOR_ena ;
--jot mstr_hr_adr_sel = mstr.hr_adr_sel;
mstr_64_trans_out = mstr.64_trans_out ;
mstr_ad_ir_ce_a = mstr.ad_ir_ce_a;
mstr_cben_ir_ce_a = mstr.cben_ir_ce_a;
mstr_cben_ir_ce_d = mstr.cben_ir_ce_d;
-- Command/byte enable Bus Signals
mstr_cbe_ce = mstr.cbe_ce ; -- Command/Byte Enable Clock Enable
mstr_low_cbe_out[3..0] = mstr.low_cbe_out[3..0]; -- Command/Byte Enable Output Registers
mstr_high_cbe_out[3..0] = mstr.high_cbe_out[3..0]; -- Command/Byte Enable Output Registers
mstr_hr_cbe_sel = mstr.hr_cbe_sel ;
mstr_cbe_HR_ena = mstr.cbe_HR_ena ;
mstr_cbe_oe = mstr.cbe_oe ; -- Command/Byte Enable Output Enable
-- Hand Shake Signals
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