📄 pci_c.tdf
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l_ldat_ackn : OUTPUT; -- Low Data Acknowledge
l_hdat_ackn : OUTPUT; -- High Data Acknowledge
-- Local Master Input Signals
-- lm_adr64n : INPUT = VCC; -- Local Master 64 Bit Address Request
lm_req32n : INPUT; -- Local Master 32-bit Request Transaction
lm_req64n : INPUT; -- Local Master 64-bit Request Transaction
lm_lastn : INPUT; -- Local Master End Transaction
lm_rdyn : INPUT; -- Local Master ready
-- Will assert waits on the next clock cycle
-- Local Master Output Signals
lm_adr_ackn : OUTPUT; -- Local Master Address Acknowledge
lm_ackn : OUTPUT; -- Master Transfer Acknowledge
-- When Asserted Indicates that Data is valid or Ready to recieve data
lm_dxfrn : OUTPUT;
lm_tsr[9..0] : OUTPUT; -- Master Transaction Status Registers
-- 0: Master is requesting the Bus
-- 1: Master has been Granted the bus
-- 2: Master is in Address Phase
-- 3: Master is Transferring data
-- 4: Latency Timer has expired
-- 5: Master Recieved a retry
-- 6: Master Recieved a Disconnect with 0 Data Transfers
-- 7: Master Recieved a Disconnect with 1 Data Transfers
-- 8: PCI data Xfr in Last Clock
-- 9: 64 bit transaction
-- Local Target Input Signals
lt_rdyn : INPUT; -- Local Target Ready
lt_abortn : INPUT; -- Instructs the Target to abort the current Transaction
lt_discn : INPUT; -- Instructs the Target to end the current Transaction with a Disconnect
-- or retry depending on the time when it was asserted
lirqn : INPUT; -- Local Interrupt Request
-- Local Target Output Signals
lt_framen : OUTPUT; -- Local Target Begin/End Transaction
lt_ackn : OUTPUT; -- Target Transfer Acknowledge
lt_dxfrn : OUTPUT; -- Target data transfer is occurring
lt_tsr[11..0] : OUTPUT; -- Target Transaction Status Registers
-- 5..0: Target Base Address Register accessed
-- 6: Target indicates an Expansion ROM hit
-- 7: Target transaction is 64 bit
-- 8: Target is accessed from PCI bus
-- lt_lackn : OUTPUT; -- Low Target Data Transfer Acknowledge
-- lt_hackn : OUTPUT; -- High Targer Data Transfer Acknowledge
-- Local Configuration Space Outputs
cmd_reg[5..0] : OUTPUT; -- PCI Configuration Command Registers Outputs
-- 0: I/O Enable ( Command Register Bit 0)
-- 1: Memory Enable ( Command Register Bit 1)
-- 2: Master Enable ( Command Register Bit 2)
-- 3: MWI Enable ( Command Register Bit 4)
-- 4: PERR Response Ena ( Command Register Bit 6)
-- 5: SERR Enable ( Command Register Bit 8)
-- Local Status Register Outputs
stat_reg[5..0] : OUTPUT; -- Status Register Outputs
-- 0: Data Parity Error Reported ( Status Register Bit 8)
-- 1: Signaled Target Abort ( Status Register Bit 11)
-- 2: Recieved Target Abort ( Status Register Bit 12)
-- 3: Recieved Master Abort ( Status Register Bit 13)
-- 4: Signaled System Error ( Status Register Bit 14)
-- 5: Detected Parit Error ( Status Register Bit 15)
-- Other Local Configuration Register Outputs
cache[7..0] : OUTPUT; -- Cache Line Register Data
)
VARIABLE
parity_Chk : pcic_pk; -- Parity Generator XOR Tree
parity_gen : pcic_pg; -- Parity Generator XOR Tree
parity_gen64 : pcic_pg; -- Parity Generator XOR Tree
trg : pcic_t; -- Instantiate Target Control Module
mstr : pcic_m; -- Instantiate Master Control Module
-- Internal Active High Input Nodes for PCI Signals
gnt : NODE; -- gnt Input
frame : NODE; -- Frame Input
irdy : NODE; -- Irdy Input
devsel : NODE; -- DEVSEL Input
trdy : NODE; -- trdy Input
stop : NODE; -- stop Input
perr : NODE; -- Parity Error Input
req64 : NODE; -- Request 64 bit
ack64 : NODE; -- Acknowledge 64 bit
-- Output Enables for PCI Signals
par_oe : NODE; -- PAR Output Enable
par_oeR : DFFE;
req64_oe : NODE; -- irdy Output enable
frame_oe : NODE; -- Frame Output Enable
irdy_oe : NODE; -- irdy Output enable
perr_oe_R : DFFE; -- PERR Output Enabel Register
-- Registered Active High PCI Signals
ad_IR_address[31..0] : DFFE; -- AD Input Register for Address
low_ad_IR_data[31..0] : DFFE; -- AD Input Register for Data
high_ad_IR_data[31..0] : DFFE; -- AD Input Register for Data
cben_IR_address[3..0] : DFFE; -- CBEN Input Register
low_cben_IR_data[3..0] : DFFE; -- CBEN Input Register
high_cben_IR_data[3..0] : DFFE; -- CBEN Input Register
-- Active High Output Registers for PCI Signals
low_ad_OR[31..0] : DFFE; -- AD Output Register
high_ad_OR[63..32] : DFFE; -- AD Output Register
low_cben_or[3..0] : DFFE; -- CBEN Output Register
high_cben_or[3..0] : DFFE; -- CBEN Output Register
par_OR : DFFE; -- PAR Output Register
par_OR64 : DFFE; -- PAR64 Output Register
frame_out : Node; -- Frame Output Signal
irdy_out : Node; -- Irdy Output Signal
req64_out : Node; -- Request 64 bit output signal
inta_OR : DFFE; -- Interrup A Output Register
req_out : NODE; -- Request Output Register
-- PCI Signals Tristate Buffers
ad_tri[63..0] : TRI; -- AD Tristate buffer
ad_tri_oe : NODE;
cbe_tri[7..0] : TRI; -- CBEN Tristate Buffer
-- Active High PCI Output Signals
-- Parity Checking Signals
-- Parity Generator Signals
par_gen_out : NODE; -- Parity Output from Parity Generator
par_gen_out64 : NODE; -- Parity Output from Parity Generator
-- Target Outputs
trg_serr_vld : LCELL;--NODE; -- SERR Error is valid
trg_perr_vld : NODE; -- Parity Error is valid
trg_perr_oe : NODE; -- PERR Output Enable
trg_par_oe : NODE; -- PAR Output Enable
--6/8 low_trg_dat_out[31..0]: NODE; -- Target Output Data to AD Output Register
-- low_trg_dat_out_lc1[31..0] : LCELL;
-- high_trg_dat_out[31..0]: NODE; -- Target Output Data to AD Output Register
-- trg_ad_ce : NODE; -- Target AD Output Registers clock Enable
trg_ad_oe : NODE; -- Target AD OE Output
trg_ad_sel : LCELL; -- AD Output Mux Select
-- ack64_oe : NODE; -- Ack64 Output Enable
ack64_out : NODE; -- Acknowledge 64 bit output signal
targ_oeR : NODE; -- Target Control Signals Output Enable
trdy_out : NODE; -- PCI Target Ready Output
devsel_out : NODE; -- PCI Device Select Output
stop_out : NODE; -- PCI Stop Output
serr_out : NODE; -- SERR Output Register
trg_ad_IR_ce_A : LCELL;--NODE; -- Target AD/BE Clock Enable- Address
trg_ad_IR_ce_D : LCELL;--NODE; -- Target AD/BE Clock Enable- Data
trg_cben_IR_ce_A : LCELL;--NODE; -- Target AD/BE Clock Enable- Address
trg_cben_IR_ce_D : LCELL;--NODE; -- Target AD/BE Clock Enable- Data
trg_low_data_out[31..0] : NODE; -- Target Local Side Low Output Data to AD Output Register
trg_high_data_out[31..0]: NODE; -- Target Local Side Low Output Data to AD Output Register
trg_cfg_dat_out[31..0] : NODE; -- Target Configuration data Output to AD Output Register
trg_cfg_cyc_out : NODE; -- Target Configuratiob Cycle Indicator
trg_hr_dat_sel : NODE; -- Target Holding Register Select Signal
trg_dati_HR_ena : NODE; -- Target Holding Register Enable Signal
trg_64_trans_out : NODE;
-- trg_adr_phase_out : NODE;
-- junk : node;
perr_rep_set : NODE;
perr_det_set : NODE;
serr_sig_set : NODE;
perr_out : Node;
io_ena : NODE; -- I/O Space Enable
mem_ena : NODE; -- Memory Space Enable
mstr_ena : NODE; -- Bus Master Enable
mwi_ena : NODE; -- Memory Write and Invalidate Enable
perr_ena : NODE; -- Pariy Error Response Enable
serr_ena : NODE; -- SERR Enable
perr_rep : NODE; -- Data Parity Error Signaled
tabort_sig : NODE; -- Signaled Target Abort
tabort_rcvd : NODE; -- Recieved Target Abort
mabort_rcvd : NODE; -- Recieved Master Abort
serr_sig : NODE; -- Signaled SERR
perr_det : NODE; -- Detected Parity Error
lat_dat[7..0] : NODE; -- Latency Timer data
-- cache[7..0] : NODE; -- Cache Line Register data
mstr_low_data_out[31..0]: NODE; -- Master Output Data to AD Output Register
mstr_high_data_out[31..0]: NODE; -- Master Output Data to AD Output Register
mstr_hr_dat_sel : NODE; -- Target Holding Register Select Signal
mstr_trg_hr_dat_sel : LCELL;
hi_low_sel : LCELL;--NODE;
mstr_dati_HR_ena : NODE; -- Target Holding Register Enable Signal
--6/8 low_mstr_dat_out[31..0] : NODE;
-- high_mstr_dat_out[31..0] : NODE;
mstr_ADOR_ena : LCELL;--NODE;
mstr_ad_oe : NODE; -- Master AD OE Output
mstr_ad_sel : LCELL; -- Master AD Output Mux Select
-- mstr_trg_ad_sel : LCELL;
mstr_ad_IR_ce_D : LCELL;--NODE; -- AD Input Register Clock Enable
mstr_cbe_oe : NODE; -- Master cbe Output enable
mstr_low_cbe_out[3..0] : NODE; -- Master Cbe output
mstr_high_cbe_out[3..0] : NODE; -- Master Cbe output
mstr_cbe_ce : LCELL;--NODE; -- master CBE Clock Enable
mstr_hr_cbe_sel : LCELL;--NODE;
mstr_cbe_HR_ena : LCELL;--NODE;
low_mstr_cbe_out[3..0] : NODE;
high_mstr_cbe_out[3..0] : NODE;
targ_abrt_set : Node;
mstr_abrt_set : NODE;
-- perr_vld : NODE;
-- stat_reg[5..0] : NODE;
low_data_out_HR[31..0] : DFFE; -- Low data holding register
low_data_out_hr_ena_d : NODE;
low_cbe_out_HR[3..0] : DFFE; -- Low Command Byte Enables holding register
high_data_out_HR[31..0] : DFFE; -- Low data holding register
high_cbe_out_HR[3..0] : DFFE; -- Low Command Byte Enables holding register
-- Local Master Active High Inputs
lm_last : NODE;
-- lm_adr64 : NODE;
lm_req64 : NODE;
lm_req32 : NODE;
lm_adr_ack : NODE;
-- Master Parity Signals
mstr_perr_vld : NODE; -- master Parity Error valid
mstr_perr_oe : NODE; -- PERR Output Enable
mstr_par_oe : NODE; -- PAR Output Enable
mstr_actv : NODE;
mstr_dac_decode : NODE;
trg_ADOR_ena : LCELL;--node;
ador_hi_dena : LCELL;--node;
m_ador_hi_dena : node;
mstr_hi_low_sel : LCELL;--node;
-- mstr_trg_hi_low_sel : LCELL;
--ad_ce : node;
-- mstr_MS_ENA : node;
-- mstr_MW_LXFR : node;
-- mstr_adr_vld : node;
-- mstr_wr_dxfr : NODE; -- Master Write Data Transfer
ad_IR_ce_data : LCELL;--node;
ad_IR_ce_address : LCELL;--node;
cben_IR_ce_data : LCELL;--node;
cben_IR_ce_address : LCELL;--node;
trg_low_ad_out_sel :node;
-- mstr_low_ad_out_sel :node;
mstr_trg_low_ad_out_sel : node;
--OPTIMIZATION high_low_ad_out_sel :node;
-- parity_ad_ir_ce_address : NODE;
-- parity_cben_ir_ce_address : NODE;
IF (TARGET_DEVICE == "EPF10K100EFC484") GENERATE
ad_ce[20..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K50EFC484") GENERATE
ad_ce[26..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K200EFC672") GENERATE
ad_ce[19..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "EPF10K130EFC484") GENERATE
ad_ce[19..0] : LCELL;
ELSE GENERATE
IF (TARGET_DEVICE == "NEW") GENERATE
ad_ce[63..0] : LCELL;
ELSE GENERATE
ad_ce[63..0] : LCELL;
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
END GENERATE;
--ad_ce : node;
ad_ce_nc : node;
ad_ce_lc : NODE;
low_ad_out[31..0] : NODE; -- AD Data MUX Ouput
low_ad_out_lc1[31..0] : LCELL;
low_ad_out_lc2[31..0] : LCELL;
-- low_ad_out_lc3[31..0] : LCELL;
mstr_trg_low : NODE;
high_ad_out[31..0] : NODE; -- AD Data MUX Ouput
high_ad_out_lc[31..0] : LCELL;
mstr_trg_hi_ad : LCELL;
--Local Data Out Signals
lt_ldata_ackn : NODE; -- Target Data Acknowledge
lt_hdata_ackn : NODE;
lm_ldata_ackn : NODE;
lm_hdata_ackn : NODE;
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