📄 pci_c.tdf
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-- ***************** Version 43 *****************
-- User: Otan Date: 12/16/98 Time: 7:33a
-- Updated in $/MegaCore/HandOff/45/source/src
-- for beta release
--
-- ***************** Version 41 *****************
-- User: Otan Date: 12/16/98 Time: 7:00a
-- Updated in $/MegaCore/HandOff/45/source/src
-- for beta release
--
-- ***************** Version 39 *****************
-- User: Otan Date: 12/15/98 Time: 9:28p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 38 *****************
-- User: Otan Date: 12/14/98 Time: 11:17p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 35 *****************
-- User: Otan Date: 12/10/98 Time: 8:09p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Ziad checked it in without figuring out what changed
--
-- ***************** Version 34 *****************
-- User: Ziada Date: 12/09/98 Time: 4:23p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 33 *****************
-- User: Otan Date: 12/08/98 Time: 4:59p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 32 *****************
-- User: Ziada Date: 12/08/98 Time: 11:40a
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 31 *****************
-- User: Otan Date: 12/04/98 Time: 10:23a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Latest signal names
--
-- ***************** Version 30 *****************
-- User: Nprasad Date: 11/30/98 Time: 5:53p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments to all the files. I'M DONE!! I'M DONE!!
--
-- ***************** Version 29 *****************
-- User: Nprasad Date: 11/30/98 Time: 3:34p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the Master Write State Machine and the relevant signals to the
-- new specification. Ran simulations and fixed several bugs.
--
-- ***************** Version 28 *****************
-- User: Nprasad Date: 11/29/98 Time: 4:23p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added capability to indicate a pure 64 bit system to. Parameter
-- 64bit_system.
--
-- ***************** Version 27 *****************
-- User: Nprasad Date: 11/29/98 Time: 3:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed lm_ack, irdy, frame and req64 to meet the new specifications
-- and logic. Also added lm_req32 as a control signal to trigger the
-- master core to request the bus.
--
-- ***************** Version 26 *****************
-- User: Nprasad Date: 11/29/98 Time: 2:31p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write State Machine is now changed to the new specification. It
-- suports:
-- 32 bit burst through lm_req32
-- 32 bit single cycle
-- 32 bit io cycle
-- 64 bit burst
-- 64 bit single cycle <-- Only if the bus contains exclusively 64 bit
-- devices
--
-- ***************** Version 25 *****************
-- User: Nprasad Date: 11/25/98 Time: 4:56p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added some comments.
--
-- ***************** Version 24 *****************
-- User: Otan Date: 11/25/98 Time: 1:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write Simulations Work.
--
-- ***************** Version 22 *****************
-- User: Otan Date: 11/23/98 Time: 7:04p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Write debugging 64-64 and 32-64.
--
-- ***************** Version 21 *****************
-- User: Otan Date: 11/23/98 Time: 3:37p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target Read Simulations successful. Added 64-bit -> 64-bit and 32-bit
-- -> 64-bit transactions.
--
-- ***************** Version 20 *****************
-- User: Nprasad Date: 11/23/98 Time: 11:32a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Fixed 32-->64 State Machine in Target.
--
-- ***************** Version 19 *****************
-- User: Otan Date: 11/20/98 Time: 7:24p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 18 *****************
-- User: Otan Date: 11/20/98 Time: 7:21p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Read Debugging
--
-- ***************** Version 17 *****************
-- User: Otan Date: 11/20/98 Time: 4:20p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 64-bit Target Write and Memory Read works with simulation, local and
-- PCI wait states.
-- Added l_ldata_ackn and l_hdata_ackn to distinguish low and high dwords
-- for 32-bit PCI.
--
-- ***************** Version 16 *****************
-- User: Otan Date: 11/19/98 Time: 1:55p
-- Updated in $/MegaCore/HandOff/45/source/src
-- 32-bit finished, except for data timeout.
--
-- ***************** Version 15 *****************
-- User: Otan Date: 11/18/98 Time: 7:51p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read/Write works for single and burst cycles for PCI and local
-- wait states.
--
-- ***************** Version 14 *****************
-- User: Otan Date: 11/17/98 Time: 10:27p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Master Read simulating successfully, except for lm_ackn
--
-- ***************** Version 13 *****************
-- User: Nprasad Date: 11/17/98 Time: 8:33p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Added 64 bit place holders for all of the files. Completed par gen and
-- parity check for 64 bit.
--
-- ***************** Version 12 *****************
-- User: Nprasad Date: 11/16/98 Time: 10:05p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed Master Datapath to the top level. Added the extra signals
-- needed.
--
-- ***************** Version 11 *****************
-- User: Otan Date: 11/16/98 Time: 2:55p
-- Updated in $/MegaCore/HandOff/45/source/src
--
-- ***************** Version 6 *****************
-- User: Nprasad Date: 11/12/98 Time: 11:49p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Changed the output data path to the top level. Change the CE for the
-- input Ad registers so that data and command are till the next cycle.
-- Changed the Target local read state machine and the rest of the signals
-- to adjust for the change in the datapath. First draft for target local
-- ren. Minor tweaks elsewhere.
--
-- ***************** Version 5 *****************
-- User: Nprasad Date: 11/11/98 Time: 10:28p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Target local write data path complete. Target local write state machine
-- complete. Signals were modified to fucntion as specified. First draft.
--
-- ***************** Version 4 *****************
-- User: Nprasad Date: 11/11/98 Time: 7:10p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Address path has changed. Data path is through a partial change.
-- New signal names added. Other superficial changes.
--
-- ***************** Version 3 *****************
-- User: Nprasad Date: 10/26/98 Time: 11:42a
-- Updated in $/MegaCore/HandOff/45/source/src
-- Removed PCI_B Comments and Optmization
--
-- ***************** Version 2 *****************
-- User: Nprasad Date: 10/22/98 Time: 4:42p
-- Updated in $/MegaCore/HandOff/45/source/src
-- Cleaned all history messages
--
--
-- ***************** Version 41 *****************
-- User: Otan Date: 10/21/98 Time: 9:41a
-- Updated in $/MegaCore/HandOff/35/source/src
-- ver3.02
--
FUNCTION pcic_m (clk, rstn, gnt, frame, irdy, trdy, devsel, stop, perr, mstr_ena, lat_dat[7..0],
lm_req64, lm_req32, lm_last, lm_rdyn, low_lm_dati[31..0], %lm_adri[31..0],% low_lm_beni[3..0], ack64, high_lm_dati[31..0],
high_lm_beni[3..0] %lm_cmd[3..0], 64bit_PCI%)--, lm_adr64)
WITH (OPTIMIZE_MSTR)
RETURNS (low_data_out[31..0], high_data_out[31..0], ad_oe, ad_sel, ad_ir_ce_D, cbe_ce, low_cbe_out[3..0], high_cbe_out[3..0], cbe_oe,
frame_out, frame_oe, irdy_out, irdy_oe, req_out, perr_vld, perr_oe, par_oe, perr_rep_set, targ_abrt_set, mstr_abrt_set,
lm_adr_ack, lm_ackn, %trdyrn,% lm_tsr[9..0], mstr_actv, hr_dat_sel, dati_HR_ena, ADOR_ena, hr_cbe_sel, cbe_HR_ena,
req64_out, req64_oe, hr_adr_sel, lm_ldata_ackn, lm_hdata_ackn, lm_dxfrn, ADOR_HI_DENA, HI_LOW_SEL, 64_trans_out, ad_ir_ce_a, cben_ir_ce_a,
cben_ir_ce_d, dac_decode_out);
FUNCTION pcic_pk (clk, rstn, par, low_ad_ir_addr[31..0], low_cben_ir_addr[3..0], low_ad_ir[31..0], low_cben_ir[3..0], par64, high_ad_ir[31..0], high_cben_ir[3..0], perr_ena,
serr_ena, mstr_perr_vld, targ_perr_vld, targ_serr_vld, trg_64_trans_out, mstr_64_trans_out%, trg_adr_phase_out, lm_adr_ackn%)
RETURNS (perr_det_set, serr_sig_set, perr_out, serr_out);
FUNCTION pcic_pg (data[31..0], cben[3..0])
RETURNS (parity);
FUNCTION pcic_t (clk, rstn, ad_ir_address[31..0], cben_ir_address[3..0], frame, irdy, idsel, low_lt_dati[31..0], lt_rdyn,
lt_discn, lt_abortn, perr_rep_set, perr_det_set, serr_sig_set, mstr_actv, mstr_abrt_set, targ_abrt_set,
lcfg_adr[7..0], lcfg_ben[3..0], lcfg_dat_in[31..0], lcfg_adr_vld, lcfg_dat_vld, lcfg_wr_rdn, req64, high_lt_dati[31..0],
%64bit_PCI,% lm_ackn, mstr_dac_decode, ad_ir_data[31..0], cben_ir_data[3..0])
WITH (Host_BRIDGE_ENA, OPTIMIZE_TARG, OPTIMIZE_ACK, DATA_TIMEOUT)
RETURNS (serr_vld, perr_vld, perr_oe, par_oe, lt_adr[63..0], lt_cmd[3..0], low_lt_ben[3..0], lt_framen,
lt_ackn, %irdyrn,% ad_oe, ad_sel, targ_oer, trdy_out, devsel_out, stop_out, high_lt_ben[3..0],
io_ena, mem_ena, mstr_ena, mwi_ena, perr_ena, serr_ena, cfg_perr_rep, cfg_tabrt_sig, cfg_tabrt_rcvd,
cfg_mabrt_rcvd, cfg_serr_sig, cfg_perr_det, lat_dat[7..0], cache_dat[7..0], %base_hit[5..0],% lt_tsr[11..0],
lt_dxfrn, lcfg_dat_out[31..0], ADOR_ena, ad_IR_ce_A, ad_IR_ce_D, cben_IR_ce_A, cben_IR_ce_D,
low_data_out[31..0], high_data_out[31..0], cfg_dat_out[31..0], cfg_cyc_out, hr_dat_sel, dati_HR_ena, ack64_out,
lt_ldata_ackn, lt_hdata_ackn, lt_sel_w, ador_hi_dena, hi_low_sel, 64_trans_out, adr_phase_out, dac_sr_out%, lt_lackn, lt_hackn%);
INCLUDE "maxplus2.inc";
PARAMETERS
(
TARGET_DEVICE = "EPF10K50EFC484",
PCI_66MHZ_CAPABLE = "YES",
HOST_BRIDGE_ENA = "NO", -- Enable Host Bridge Support
INTERNAL_ARBITER = "NO", -- Determines if REQ signal should have a tristate buffer or not.
VENDOR_ID = H"1172", -- Vendor ID Register
DEVICE_ID = H"0004", -- Device ID Register
REVISION_ID = H"01", -- Revision ID Register
CLASS_CODE = H"FF0000", -- Class Code Register
SUBSYSTEM_ID = H"0000", -- Subsystem ID Register
SUBSYSTEM_VENDOR_ID = H"0000", -- Subsystem Vendor ID Register
MIN_GRANT = H"00", -- Minimum Grant Register
MAX_LATENCY = H"00", -- Maximum Latency Register
CAP_LIST_ENA = "NO", -- Capabilities List
CAP_PTR = H"40",
EXP_ROM_ENA = "NO",
EXP_ROM_BAR = H"FFF00000", -- EXpansion ROM Base Address Register
USE_EXP_ROM_DEFAULT = "NO", -- Use The Expansion ROM BAR
EXP_ROM_DEFAULT = H"FFF00000", -- Expansion ROM Power Up Value
NUMBER_OF_BARS = 1, -- Number of Base Address Regisers to be used
BAR0 = H"FFF00000", -- Values in CFG_BAR0
BAR1 = H"FFF00000", -- Bit(0) = 0-Memory, 1-I/O Space
BAR2 = H"FFF00000", -- Bit(1) = Reserve for I/O Space
BAR3 = H"FFF00000", -- Bit(2,1) = Memory Type
BAR4 = H"FFF00000", -- Bit(3) = Prefetchable Memory Address
BAR5 = H"FFF00000", -- Bits(31..n) = 1 for number of decode bits
DUAL_ADDRESS_ENA = "YES",
64BIT_SYSTEM = "NO", -- Indicates whether this is a pure 64bit system or not
LOCAL_CONFIG_ENA = "NO", -- Enable Host Bridge Support
CORE = "MASTER", -- Type of Core interface used
DATA_TIMEOUT = 16 -- Load value for time counter on target
);
CONSTANT REVISION="VER 1.1 $Revision: 115 $, $JustDate: 6/17/99 $";
SUBDESIGN 'pci_c'
(
-- PCI Input Signals
clk : INPUT; -- PCI Clock
rstn : INPUT; -- PCI Reset
gntn : INPUT; -- PCI Grant
idsel : INPUT; -- PCI ID Select
-- PCI Output Signals
intan : OUTPUT; -- PCI Interrupt A
reqn : OUTPUT; -- PCI Request
serrn : OUTPUT; -- PCI System Error
-- PCI Bidir Signals
ad[63..0] : BIDIR; -- PCI Address/Data Bus
cben[7..0] : BIDIR; -- PCI Command/Byte Enables
par : BIDIR; -- PCI Parity
par64 : BIDIR; -- PCI Parity for Upper 32 bits
perrn : BIDIR; -- PCI Data Parity Error
-- framen : BIDIR; -- PCI Frame Signal
-- req64n : BIDIR; -- PCI 64 bit request
-- irdyn : BIDIR; -- PCI Initiator Ready
-- trdyn : BIDIR; -- PCI Target Ready
-- devseln : BIDIR; -- PCI Device Select
-- ack64n : BIDIR; -- PCI 64 acknowledge signal
-- stopn : BIDIR; -- PCI Transaction Stop
framen_in : INPUT; -- PCI Frame Signal INPUT
req64n_in : INPUT; -- PCI 64 bit request
irdyn_in : INPUT; -- PCI Initiator Ready INPUT
trdyn_in : INPUT; -- PCI Target Ready INPUT
devseln_in : INPUT; -- PCI Device Select
ack64n_in : INPUT; -- PCI 64 acknowledge signal
stopn_in : INPUT; -- PCI Transaction Stop
framen_out : OUTPUT; -- PCI Frame Signal OUTPUT
req64n_out : OUTPUT; -- PCI 64 bit request
irdyn_out : OUTPUT; -- PCI Initiator Ready OUTPUT
trdyn_out : OUTPUT; -- PCI Target Ready OUTPUT
devseln_out : OUTPUT; -- PCI Device Select
ack64n_out : OUTPUT; -- PCI 64 acknowledge signal
stopn_out : OUTPUT; -- PCI Transaction Stop
-- Local Address, Data, Command and Byte Enables
--IF (DUAL_ADDRESS_ENA == "NO" ) GENERATE
-- l_dati[63..0] : INPUT; -- Target Data Input
-- l_adri[31..0] : INPUT; -- Local Side Master Address/Data Bus
-- l_cmdi[3..0] : INPUT; -- Local Command
-- l_beni[7..0] : INPUT; -- Local Byte Enables
--ELSE GENERATE
l_adi[63..0] : INPUT; -- Local Side Address/Data Bus version 1.1
l_cbeni[7..0] : INPUT; -- Local Side Command/Byte Enable Bus version 1.1
--ELSE GENERATE;
l_adro[63..0] : OUTPUT; -- Target Address Output
l_dato[63..0] : OUTPUT; -- Target Data Output
l_beno[7..0] : OUTPUT; -- Target Byte Enable
l_cmdo[3..0] : OUTPUT; -- Target command
-- General Purpose Outputs
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