lvds.tan.rpt

nios系统下LVDS的ip源码

; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll:bs2_pll|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk_i    ; 1                     ; 2                   ; -2.203 ns ;              ;
; pll:bs2_pll|altpll:altpll_component|_clk1 ;                    ; PLL output ; 200.0 MHz        ; 0.000 ns      ; 0.000 ns     ; clk_i    ; 4                     ; 1                   ; -2.203 ns ;              ;
; clk_i                                     ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP              ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll:bs2_pll|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                     ;
+-----------+-----------------------------------------------+---------------------------------------------------------------------------------------------------------------+----------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack     ; Actual fmax (period)                          ; From                                                                                                          ; To                   ; From Clock                                ; To Clock                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+---------------------------------------------------------------------------------------------------------------+----------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 3.829 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg1|shift_reg[1] ; data_reveive[3]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.907 ns                ;
; 3.977 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg2|shift_reg[0] ; data_reveive[0]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.759 ns                ;
; 3.979 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg1|shift_reg[2] ; data_reveive[5]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.757 ns                ;
; 3.979 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg2|shift_reg[1] ; data_reveive[2]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.757 ns                ;
; 3.980 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg1|shift_reg[3] ; data_reveive[7]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.756 ns                ;
; 3.981 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg2|shift_reg[2] ; data_reveive[4]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.755 ns                ;
; 3.981 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg1|shift_reg[0] ; data_reveive[1]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.755 ns                ;
; 3.983 ns  ; None                                          ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg2|shift_reg[3] ; data_reveive[6]~reg0 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.736 ns                  ; 0.753 ns                ;
; 37.194 ns ; 356.38 MHz ( period = 2.806 ns )              ; tr_reg[1]~reg0                                                                                                ; tr_reg[7]~reg0       ; pll:bs2_pll|altpll:altpll_component|_clk0 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 2.542 ns                ;
; 37.280 ns ; 367.65 MHz ( period = 2.720 ns )              ; tr_reg[1]~reg0                                                                                                ; tr_reg[6]~reg0       ; pll:bs2_pll|altpll:altpll_component|_clk0 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 2.456 ns                ;
; 37.366 ns ; 379.65 MHz ( period = 2.634 ns )              ; tr_reg[1]~reg0                                                                                                ; tr_reg[5]~reg0       ; pll:bs2_pll|altpll:altpll_component|_clk0 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 2.370 ns                ;
; 37.516 ns ; 402.58 MHz ( period = 2.484 ns )              ; tr_reg[4]~reg0                                                                                                ; tr_reg[7]~reg0       ; pll:bs2_pll|altpll:altpll_component|_clk0 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 2.220 ns                ;
; 37.555 ns ; Restricted to 402.58 MHz ( period = 2.48 ns ) ; tr_reg[0]~reg0                                                                                                ; tr_reg[7]~reg0       ; pll:bs2_pll|altpll:altpll_component|_clk0 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 2.181 ns                ;