lvds.tan.rpt

来自「nios系统下LVDS的ip源码」· RPT 代码 · 共 201 行 · 第 1/5 页

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; Clock Setup: 'pll:bs2_pll|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+--------------------------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                    ; To                                                                                                                                                                                                                      ; From Clock                                ; To Clock                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time                    ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+--------------------------------------------+
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg17                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg16                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg15                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg14                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg13                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg12                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg11                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg10                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg9                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg8                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg7                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg6                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg5                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg4                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg3                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg2                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg1                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg6                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg5                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg4                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg3                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg2                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg1                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_address_reg0                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg0                                                                            ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[1]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg17                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[1]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg16                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[1]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg15                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[1]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg14                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[1]                                       ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg13                                                                           ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 5.000 ns                    ; N/A                       ; Restricted to 6.13 ns ( period = 6.13 ns ) ;
; N/A                                     ; Restricted to 163.03 MHz ( period = 6.13 ns )       ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|