lvds.tan.rpt

nios系统下LVDS的ip源码

Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Type                                                     ; Slack     ; Required Time                    ; Actual Time                                    ; From                                                                                                                                                                              ; To                                                                                                                                                                                                    ; From Clock                                ; To Clock                                  ; Failed Paths ;
+----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Worst-case tsu                                           ; N/A       ; None                             ; 7.984 ns                                       ; reset_n                                                                                                                                                                           ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[9]                                                                                                                                                  ; --                                        ; clk_i                                     ; 0            ;
; Worst-case tco                                           ; N/A       ; None                             ; 6.236 ns                                       ; data_reveive[2]~reg0                                                                                                                                                              ; data_reveive[2]                                                                                                                                                                                       ; clk_i                                     ; --                                        ; 0            ;
; Worst-case tpd                                           ; N/A       ; None                             ; 3.106 ns                                       ; altera_internal_jtag~TDO                                                                                                                                                          ; altera_reserved_tdo                                                                                                                                                                                   ; --                                        ; --                                        ; 0            ;
; Worst-case th                                            ; N/A       ; None                             ; 2.411 ns                                       ; altera_internal_jtag                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[53] ; --                                        ; altera_internal_jtag~TCKUTAP              ; 0            ;
; Worst-case Minimum Pulse Width Requirement (Low)         ; -0.567 ns ; 3.067 ns                         ; 2.500 ns                                       ; pll:bs2_pll|altpll:altpll_component|_clk1                                                                                                                                         ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg0                                                          ; --                                        ; --                                        ; 43           ;
; Worst-case Minimum Pulse Width Requirement (High)        ; -0.567 ns ; 3.067 ns                         ; 2.500 ns                                       ; pll:bs2_pll|altpll:altpll_component|_clk1                                                                                                                                         ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg0                                                          ; --                                        ; --                                        ; 43           ;
; Clock Setup: 'pll:bs2_pll|altpll:altpll_component|_clk1' ; N/A       ; 200.00 MHz ( period = 5.000 ns ) ; Restricted to 163.03 MHz ( period = 6.134 ns ) ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0] ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg17                                                         ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 75           ;
; Clock Setup: 'pll:bs2_pll|altpll:altpll_component|_clk0' ; 3.829 ns  ; 25.00 MHz ( period = 40.000 ns ) ; N/A                                            ; rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg1|shift_reg[1]                                                                     ; data_reveive[3]~reg0                                                                                                                                                                                  ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'              ; N/A       ; None                             ; 90.66 MHz ( period = 11.030 ns )               ; sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0]                                                                                                                   ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                                                                          ; altera_internal_jtag~TCKUTAP              ; altera_internal_jtag~TCKUTAP              ; 0            ;
; Clock Hold: 'pll:bs2_pll|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 25.00 MHz ( period = 40.000 ns ) ; N/A                                            ; tr_reg[0]~reg0                                                                                                                                                                    ; tr_reg[0]~reg0                                                                                                                                                                                        ; pll:bs2_pll|altpll:altpll_component|_clk0 ; pll:bs2_pll|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'pll:bs2_pll|altpll:altpll_component|_clk1'  ; 0.499 ns  ; 200.00 MHz ( period = 5.000 ns ) ; N/A                                            ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena                              ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena                                                  ; pll:bs2_pll|altpll:altpll_component|_clk1 ; pll:bs2_pll|altpll:altpll_component|_clk1 ; 0            ;
; Other violations (see messages)                          ;           ;                                  ;                                                ;                                                                                                                                                                                   ;                                                                                                                                                                                                       ;                                           ;                                           ; 1            ;
; Total number of failed paths                             ;           ;                                  ;                                                ;                                                                                                                                                                                   ;                                                                                                                                                                                                       ;                                           ;                                           ; 162          ;
+----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C5Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;