comparador.vhd

用VHDL实现视频控制程序,实现对图像的采集和压缩,

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity COMPARADOR is
     generic (ANCHO: integer := 8;
              EOS : integer := 200;
              SOB : integer := 210;
              EOB : integer := 220;
              EOL : integer := 230 
     );
     port ( data : in std_logic_vector (ANCHO-1 downto 0);
            clk, resetz,href : in std_logic;
            O1, O2, O3 : out std_logic
          );
end COMPARADOR;

architecture comp_arch of comparador is
signal p1,p2,p3: std_logic;
begin

--Proceso de sincronismo

sinc: process(clk,resetz)
 begin
     if(resetz='0')then
      O1<='0';
      O2<='0';
      O3<='0';
     elsif(clk'event and clk='1')then
      O1<=p1;
      O2<=p2;
      O3<=p3;
     end if;
end process sinc;

comp:process(data,href)
begin
    if(data>EOS)then
      p1<='1';
    else
      p1<='0';
    end if;
    if(data>SOB and data<EOB)then     --Este bloque genera el hsync, vsync
      p2<='1';
    else
      p2<='0';
    end if;
    if(data>=EOL and href='0')then
      p3<='1';
    else
      p3<='0';
    end if;
end process comp;
end comp_arch;