📄 registro_pixel.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
entity registro_pixel is
generic ( N:integer:=8 );
port (
PIXEL_IN: in STD_LOGIC_VECTOR (N-1 downto 0);
PIXEL_OUT: out STD_LOGIC_VECTOR (N-1 downto 0);
Enable: in STD_LOGIC;
clk: in STD_LOGIC;
resetz: in STD_LOGIC
);
end registro_pixel;
architecture registro_pixel_arch of registro_pixel is
signal salida, p_salida: std_logic_vector(N-1 downto 0);
begin
sinc: process(resetz,clk)
begin
if(resetz='0')then
salida<=(OTHERS=>'0');
elsif(clk'event and clk='1')then
salida<=p_salida;
end if;
end process sinc;
PIXEL_OUT<=salida;
registro: process(PIXEL_IN,enable,salida)
begin
if(enable='1')then
p_salida<=PIXEL_IN;
else
p_salida<=salida;
end if;
end process registro;
end registro_pixel_arch;
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