dds.tan.qmsg

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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "WR memory RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_datain_reg0 memory RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_memory_reg0 197.01 MHz 5.076 ns Internal " "Info: Clock \"WR\" has Internal fmax of 197.01 MHz between source memory \"RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_datain_reg0\" and destination memory \"RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_memory_reg0\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_datain_reg0 1 MEM M4K_X17_Y6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_datain_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 257 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_memory_reg0 2 MEM M4K_X17_Y6 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y6; Fanout = 0; MEM Node = 'RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_memory_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 257 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 7.714 ns + Shortest memory " "Info: + Shortest clock path from clock \"WR\" to destination memory is 7.714 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns WR 1 CLK PIN_177 2072 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_177; Fanout = 2072; CLK Node = 'WR'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 248 296 464 264 "WR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.537 ns) + CELL(0.708 ns) 7.714 ns RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_memory_reg0 2 MEM M4K_X17_Y6 0 " "Info: 2: + IC(5.537 ns) + CELL(0.708 ns) = 7.714 ns; Loc. = M4K_X17_Y6; Fanout = 0; MEM Node = 'RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_memory_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.245 ns" { WR RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 257 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 28.22 % ) " "Info: Total cell delay = 2.177 ns ( 28.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.537 ns ( 71.78 % ) " "Info: Total interconnect delay = 5.537 ns ( 71.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.714 ns" { WR RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.714 ns" { WR WR~out0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 0.000ns 5.537ns } { 0.000ns 1.469ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR source 7.728 ns - Longest memory " "Info: - Longest clock path from clock \"WR\" to source memory is 7.728 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns WR 1 CLK PIN_177 2072 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_177; Fanout = 2072; CLK Node = 'WR'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 248 296 464 264 "WR" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.537 ns) + CELL(0.722 ns) 7.728 ns RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_datain_reg0 2 MEM M4K_X17_Y6 1 " "Info: 2: + IC(5.537 ns) + CELL(0.722 ns) = 7.728 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'RAM256:inst3\|altsyncram:Mem_rtl_0\|altsyncram_hle1:auto_generated\|ram_block1a7~porta_datain_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.259 ns" { WR RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 257 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 28.35 % ) " "Info: Total cell delay = 2.191 ns ( 28.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.537 ns ( 71.65 % ) " "Info: Total interconnect delay = 5.537 ns ( 71.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.728 ns" { WR RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.728 ns" { WR WR~out0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 } { 0.000ns 0.000ns 5.537ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.714 ns" { WR RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.714 ns" { WR WR~out0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 0.000ns 5.537ns } { 0.000ns 1.469ns 0.708ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.728 ns" { WR RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.728 ns" { WR WR~out0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 } { 0.000ns 0.000ns 5.537ns } { 0.000ns 1.469ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 257 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 257 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg0 RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } } { "d:/program files/altera/quartus60/win