dds.tan.qmsg

来自「基于fpga」· QMSG 代码 · 共 7 行 · 第 1/5 页

QMSG
7
字号
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DDS -c DDS --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DDS -c DDS --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "fpgaclk " "Info: Assuming node \"fpgaclk\" is an undefined clock" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 400 88 256 416 "fpgaclk" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "fpgaclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 248 296 464 264 "WR" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node \"ALE\" is an undefined clock" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 232 296 464 248 "ALE" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}

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