📄 ddr_sdram.srr
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DATAOUT[98] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[99] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[100] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[101] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[102] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[103] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[104] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[105] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[106] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[107] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[108] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[109] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[110] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[111] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[112] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[113] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[114] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[115] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[116] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[117] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[118] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[119] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[120] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[121] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[122] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[123] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[124] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[125] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[126] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[127] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[0] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[1] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[2] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[3] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[4] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[5] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[6] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQM[7] clk200_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DQS[0] System 0.0 <-2000.0 5.0 >2000.0
DQS[1] System 0.0 <-2000.0 5.0 >2000.0
DQS[2] System 0.0 <-2000.0 5.0 >2000.0
DQS[3] System 0.0 <-2000.0 5.0 >2000.0
DQS[4] System 0.0 <-2000.0 5.0 >2000.0
DQS[5] System 0.0 <-2000.0 5.0 >2000.0
DQS[6] System 0.0 <-2000.0 5.0 >2000.0
DQS[7] System 0.0 <-2000.0 5.0 >2000.0
DQ[0] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[1] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[2] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[3] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[4] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[5] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[6] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[7] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[8] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[9] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[10] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[11] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[12] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[13] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[14] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[15] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[16] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[17] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[18] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[19] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[20] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[21] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[22] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[23] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[24] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[25] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[26] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[27] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[28] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[29] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[30] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[31] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[32] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[33] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[34] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[35] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[36] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[37] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[38] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[39] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[40] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[41] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[42] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[43] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[44] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[45] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[46] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[47] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[48] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[49] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[50] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[51] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[52] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[53] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[54] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[55] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[56] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[57] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[58] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[59] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[60] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[61] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[62] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
DQ[63] clk200_inferred_clock [falling] 0.0 8.1 5.0 -3.1
RAS_N clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[0] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[1] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[2] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[3] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[4] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[5] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[6] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[7] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[8] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[9] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[10] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
SA[11] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
WE_N clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
=====================================================================================================
Detailed Timing Report for clock : clk100_inferred_clock
*******************************************
Requested Period 5.0 ns
Estimated Period 12.7 ns
Worst Slack -7.7 ns
Start Points for Paths with Slack Worse than -7.0 ns :
Arrival
Instance Type Pin Net Time Slack
---------------------------------------------------------------------
RESET_N Port RESET_N RESET_N_in_in 0.0 -7.7
=====================================================================
End Points for Paths with Slack Worse than -7.0 ns :
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