📄 ddr_sdram.srr
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DQ[36] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[37] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[38] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[39] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[40] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[41] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[42] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[43] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[44] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[45] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[46] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[47] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[48] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[49] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[50] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[51] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[52] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[53] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[54] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[55] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[56] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[57] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[58] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[59] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[60] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[61] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[62] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
DQ[63] clk200_inferred_clock [falling] 0.0 0.0 0.1 0.1
RESET_N clk100_inferred_clock [rising] 0.0 0.0 -7.7 -7.7
===================================================================================================
Output Ports:
Port Reference User Arrival Required
Name Clock Constraint Time Time Slack
-----------------------------------------------------------------------------------------------------
BA[0] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
BA[1] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
CAS_N clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
CKE clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
CMDACK clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
CS_N[0] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
CS_N[1] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[0] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[1] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[2] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[3] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[4] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[5] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[6] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[7] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[8] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[9] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[10] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[11] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[12] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[13] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[14] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[15] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[16] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[17] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[18] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[19] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[20] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[21] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[22] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[23] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[24] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[25] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[26] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[27] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[28] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[29] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[30] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[31] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[32] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[33] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[34] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[35] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[36] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[37] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[38] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[39] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[40] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[41] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[42] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[43] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[44] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[45] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[46] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[47] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[48] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[49] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[50] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[51] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[52] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[53] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[54] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[55] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[56] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[57] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[58] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[59] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[60] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[61] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[62] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[63] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[64] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[65] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[66] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[67] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[68] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[69] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[70] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[71] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[72] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[73] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[74] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[75] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[76] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[77] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[78] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[79] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[80] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[81] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[82] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[83] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[84] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[85] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[86] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[87] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[88] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[89] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[90] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[91] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[92] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[93] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[94] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[95] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[96] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
DATAOUT[97] clk100_inferred_clock [rising] 0.0 5.6 5.0 -0.6
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