ddr_sdram.tlg

DDR sdram 包含的完整的源码,仿真的相关文件

Synthesizing work.ddr_sdram.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_sdram.vhd":131:14:131:16|Port direction mismatch between component and entity
Synthesizing work.pll1.syn_black_box
Post processing for work.pll1.syn_black_box
Synthesizing work.ddr_data_path.rtl
Post processing for work.ddr_data_path.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal din2a[31:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal dq2[15:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal dmin2a[3:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":141:8:141:9|Feedback mux created for signal dm1[1:0]. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":173:9:173:10|Feedback mux created for signal d2_oe. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_data_path.vhd":100:8:100:9|Feedback mux created for signal dataout[31:0]. Did you forget the set/reset assignment for this signal?
Synthesizing work.ddr_command.rtl
Post processing for work.ddr_command.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(7) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":271:9:271:10|Optimizing register bit rw_shift(3) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":271:9:271:10|Optimizing register bit rw_shift(2) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(6) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(5) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":214:9:214:10|Optimizing register bit oe_shift(4) to a constant 0
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":52:2:52:4|Input nop is unused
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":58:2:58:6|Input sc_cl is unused
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_command.vhd":60:2:60:7|Input sc_rrd is unused
Synthesizing work.ddr_control_interface.rtl
Post processing for work.ddr_control_interface.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":93:9:93:10|Feedback mux created for signal load_reg1. Did you forget the set/reset assignment for this signal?
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_control_interface.vhd":93:9:93:10|Feedback mux created for signal load_reg2. Did you forget the set/reset assignment for this signal?
Post processing for work.ddr_sdram.rtl