📄 stdlogar.vhd
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end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
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