📄 mt46v4m16.vhd
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--
-- File Name: MT46V4M16.VHD
-- Version: 0.0f
-- Date: May 24th, 1999
-- Model: Behavioral
-- Simulator: Model Technology VLOG (PC version 5.2e PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: sphuynh@micron.com
-- Company: Micron Technology, Inc.
-- Part Number: MT46V4M16 (1 Mb x 16 x 4 Banks)
--
-- Description: Micron 64 Mb SDRAM DDR (Double Data Rate)
--
-- Limitation: - Doesn't check for 4096-cycle refresh
--
-- Note: - Set simulator resolution to "ps" accuracy
-- - Model assume Clk and Clk# crossing at both edge
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0f Son P. Huynh 05/24/1999 Fix DQS not properly HiZ after
-- Micron Technology, Inc. precharge or burst terminate.
-- Fix DQS not properly go LOW if Read
-- immediate after precharge or burst term
-- Add detection for interrupting Read
-- or Write with Auto Precharge.
--
-- 0.0d Son P. Huynh 05/13/1999 First Release (from MT46V8M8.VHD)
-- Micron Technology, Inc. - Now using VHDL 1076-93 (SHARED)
-- - New testbench
-----------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.mti_pkg.ALL;
ENTITY mt46v4m16 IS
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
Clk : IN STD_LOGIC := '0';
Clk_n : IN STD_LOGIC := '1';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '0';
Cas_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt46v4m16;
ARCHITECTURE behave OF mt46v4m16 IS
TYPE State IS (ACT, A_REF, BST, EMR, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array7xB IS ARRAY (6 DOWNTO 0) OF BIT;
TYPE Array7x2BV IS ARRAY (6 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array7xCBV IS ARRAY (6 DOWNTO 0) OF BIT_VECTOR (col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (6 DOWNTO 0) OF State;
SIGNAL Operation, Rw_command : State := NOP;
SIGNAL Bank, Bank_dqs, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row, Row_dqs : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_dqs : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_brst, Col_brst_dqs : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SHARED VARIABLE Burst_counter : INTEGER := 0;
SHARED VARIABLE Data_in_enable : BIT := '0';
SHARED VARIABLE Data_out_enable : BIT := '0';
SHARED VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
SHARED VARIABLE Col_addr : Array7xCBV;
SHARED VARIABLE Bank_addr : Array7x2BV;
SHARED VARIABLE WR_chk : Array4xI;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_25, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Sys_clk, CkeZ : BIT := '0';
SIGNAL Dqs_int, Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Ext_mode_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND TO_BIT(Ba(0)) AND NOT(TO_BIT(Ba(1)));
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(TO_BIT(Ba(0))) AND NOT(TO_BIT(Ba(1))) AND TO_BIT(Addr(5));
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
Dqs <= Dqs_out;
-- System Clock
int_clk : PROCESS (Clk, Clk_n)
VARIABLE ClkZ : BIT := '0';
begin
IF Clk = '1' AND Clk_n = '0' THEN
ClkZ := '1';
CkeZ <= TO_BIT(Cke, '1');
ELSIF Clk = '0' AND Clk_n = '1' THEN
ClkZ := '0';
END IF;
Sys_clk <= CkeZ AND ClkZ;
END PROCESS;
state_register : PROCESS
VARIABLE Command : Array_state;
VARIABLE Dll_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
VARIABLE Bank_precharge : Array7x2BV;
VARIABLE A10_precharge : Array7xB;
VARIABLE Auto_precharge : Array4xB;
VARIABLE Read_precharge : Array4xB;
VARIABLE Write_precharge : Array4xB;
VARIABLE Count_precharge : Array4xI;
-- Timing Check
VARIABLE DLL_chk : INTEGER := 0;
VARIABLE MRD_chk : TIME := 0 ns;
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk, RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
BEGIN
WAIT ON Sys_clk;
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := Command(4);
Command(4) := Command(5);
Command(5) := Command(6);
Command(6) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := Col_addr(4);
Col_addr(4) := Col_addr(5);
Col_addr(5) := Col_addr(6);
Col_addr(6) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := Bank_addr(4);
Bank_addr(4) := Bank_addr(5);
Bank_addr(5) := Bank_addr(6);
Bank_addr(6) := (OTHERS => '0');
-- Precharge Pipeline
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := Bank_precharge(4);
Bank_precharge(4) := Bank_precharge(5);
Bank_precharge(5) := Bank_precharge(6);
Bank_precharge(6) := (OTHERS => '0');
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := A10_precharge(4);
A10_precharge(4) := A10_precharge(5);
A10_precharge(5) := A10_precharge(6);
A10_precharge(6) := '0';
-- tWR Counter
WR_chk(0) := WR_chk(0) + 1;
WR_chk(1) := WR_chk(1) + 1;
WR_chk(2) := WR_chk(2) + 1;
WR_chk(3) := WR_chk(3) + 1;
-- Commands Operation Decode
IF Sys_clk = '1' THEN
-- Operation Decode
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Ext_mode_enable = '1' THEN
Operation <= EMR;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- tMRD Counter
MRD_chk := MRD_chk + tCK;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1')
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Extended Load Mode Register
IF Ext_mode_enable = '1' THEN
IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN
IF Addr(0) = '0' THEN
Dll_enable := '1';
ELSE
Dll_enable := '0';
END IF;
-- LMR/EMR to EMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Extended Mode Register"
SEVERITY WARNING;
ELSE
ASSERT (FALSE)
REPORT "All bank must be Precharge before Extended Mode Register"
SEVERITY WARNING;
END IF;
-- Record current tMRD time
MRD_chk := 0 ns;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b0 /= '1' OR Pc_b1 /= '1' OR Pc_b2 /= '1' OR Pc_b3 /= '1') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- LMR/ELMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0 ns;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
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