vh_syn.tan.qmsg

标准电视信号的同步生成程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "gclk " "Info: Assuming node \"gclk\" is an undefined clock" {  } { { "vh_syn.gdf" "" { Schematic "D:/altera/qdesigns50/VH_SYN/vh_syn.gdf" { { 216 64 232 232 "gclk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "gclk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "gclk register lpm_counter:2\|dffs\[6\] register lpm_counter:2\|dffs\[11\] 100.0 MHz 10.0 ns Internal " "Info: Clock \"gclk\" has Internal fmax of 100.0 MHz between source register \"lpm_counter:2\|dffs\[6\]\" and destination register \"lpm_counter:2\|dffs\[11\]\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:2\|dffs\[6\] 1 REG LC4 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 17; REG Node = 'lpm_counter:2\|dffs\[6\]'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "" { lpm_counter:2|dffs[6] } "NODE_NAME" } "" } } { "LPM_COUNTER.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns lpm_counter:2\|dffs\[11\] 2 REG LC16 10 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC16; Fanout = 10; REG Node = 'lpm_counter:2\|dffs\[11\]'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "6.000 ns" { lpm_counter:2|dffs[6] lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "LPM_COUNTER.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns 83.33 % " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 16.67 % " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "6.000 ns" { lpm_counter:2|dffs[6] lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { lpm_counter:2|dffs[6] lpm_counter:2|dffs[11] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"gclk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns gclk 1 CLK PIN_89 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_89; Fanout = 22; CLK Node = 'gclk'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "" { gclk } "NODE_NAME" } "" } } { "vh_syn.gdf" "" { Schematic "D:/altera/qdesigns50/VH_SYN/vh_syn.gdf" { { 216 64 232 232 "gclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:2\|dffs\[11\] 2 REG LC16 10 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC16; Fanout = 10; REG Node = 'lpm_counter:2\|dffs\[11\]'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "0.000 ns" { gclk lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "LPM_COUNTER.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out lpm_counter:2|dffs[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"gclk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns gclk 1 CLK PIN_89 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_89; Fanout = 22; CLK Node = 'gclk'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "" { gclk } "NODE_NAME" } "" } } { "vh_syn.gdf" "" { Schematic "D:/altera/qdesigns50/VH_SYN/vh_syn.gdf" { { 216 64 232 232 "gclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:2\|dffs\[6\] 2 REG LC4 17 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 17; REG Node = 'lpm_counter:2\|dffs\[6\]'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "0.000 ns" { gclk lpm_counter:2|dffs[6] } "NODE_NAME" } "" } } { "LPM_COUNTER.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk lpm_counter:2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out lpm_counter:2|dffs[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out lpm_counter:2|dffs[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk lpm_counter:2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out lpm_counter:2|dffs[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "LPM_COUNTER.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "LPM_COUNTER.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/LPM_COUNTER.tdf" 262 9 0 } }  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "6.000 ns" { lpm_counter:2|dffs[6] lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { lpm_counter:2|dffs[6] lpm_counter:2|dffs[11] } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk lpm_counter:2|dffs[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out lpm_counter:2|dffs[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk lpm_counter:2|dffs[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out lpm_counter:2|dffs[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "gclk HD syn_gen:1\|hd 5.000 ns register " "Info: tco from clock \"gclk\" to destination pin \"HD\" through register \"syn_gen:1\|hd\" is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "gclk source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"gclk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns gclk 1 CLK PIN_89 22 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_89; Fanout = 22; CLK Node = 'gclk'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "" { gclk } "NODE_NAME" } "" } } { "vh_syn.gdf" "" { Schematic "D:/altera/qdesigns50/VH_SYN/vh_syn.gdf" { { 216 64 232 232 "gclk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns syn_gen:1\|hd 2 REG LC1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 1; REG Node = 'syn_gen:1\|hd'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "0.000 ns" { gclk syn_gen:1|hd } "NODE_NAME" } "" } } { "syn_gen.vhd" "" { Text "D:/altera/qdesigns50/VH_SYN/syn_gen.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk syn_gen:1|hd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out syn_gen:1|hd } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "syn_gen.vhd" "" { Text "D:/altera/qdesigns50/VH_SYN/syn_gen.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns syn_gen:1\|hd 1 REG LC1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 1; REG Node = 'syn_gen:1\|hd'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "" { syn_gen:1|hd } "NODE_NAME" } "" } } { "syn_gen.vhd" "" { Text "D:/altera/qdesigns50/VH_SYN/syn_gen.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns HD 2 PIN PIN_4 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'HD'" {  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { syn_gen:1|hd HD } "NODE_NAME" } "" } } { "vh_syn.gdf" "" { Schematic "D:/altera/qdesigns50/VH_SYN/vh_syn.gdf" { { 200 768 944 216 "HD" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { syn_gen:1|hd HD } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { syn_gen:1|hd HD } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}  } { { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { gclk syn_gen:1|hd } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { gclk gclk~out syn_gen:1|hd } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" "" { Report "D:/altera/qdesigns50/VH_SYN/db/vh_syn_cmp.qrpt" Compiler "vh_syn" "UNKNOWN" "V1" "D:/altera/qdesigns50/VH_SYN/db/vh_syn.quartus_db" { Floorplan "D:/altera/qdesigns50/VH_SYN/" "" "1.500 ns" { syn_gen:1|hd HD } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { syn_gen:1|hd HD } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 10 14:22:31 2007 " "Info: Processing ended: Sun Jun 10 14:22:31 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}