vh_syn.tan.rpt

标准电视信号的同步生成程序

; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[15] ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[14] ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[13] ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[12] ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[11] ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[10] ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[9]  ; syn_gen:1|clr          ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 100.00 MHz ( period = 10.000 ns )                   ; lpm_counter:2|dffs[0]  ; lpm_counter:2|dffs[0]  ; gclk       ; gclk     ; None                        ; None                      ; 6.000 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                        ;                        ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------+
; tco                                                                ;
+-------+--------------+------------+--------------+----+------------+
; Slack ; Required tco ; Actual tco ; From         ; To ; From Clock ;
+-------+--------------+------------+--------------+----+------------+
; N/A   ; None         ; 5.000 ns   ; syn_gen:1|hd ; HD ; gclk       ;
; N/A   ; None         ; 5.000 ns   ; syn_gen:1|vd ; VD ; gclk       ;
+-------+--------------+------------+--------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Jun 10 14:22:31 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vh_syn -c vh_syn
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "gclk" is an undefined clock
Info: Clock "gclk" has Internal fmax of 100.0 MHz between source register "lpm_counter:2|dffs[6]" and destination register "lpm_counter:2|dffs[11]" (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 17; REG Node = 'lpm_counter:2|dffs[6]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC16; Fanout = 10; REG Node = 'lpm_counter:2|dffs[11]'
        Info: Total cell delay = 5.000 ns ( 83.33 % )
        Info: Total interconnect delay = 1.000 ns ( 16.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "gclk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_89; Fanout = 22; CLK Node = 'gclk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC16; Fanout = 10; REG Node = 'lpm_counter:2|dffs[11]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "gclk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_89; Fanout = 22; CLK Node = 'gclk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 17; REG Node = 'lpm_counter:2|dffs[6]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock "gclk" to destination pin "HD" through register "syn_gen:1|hd" is 5.000 ns
    Info: + Longest clock path from clock "gclk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_89; Fanout = 22; CLK Node = 'gclk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 1; REG Node = 'syn_gen:1|hd'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 1; REG Node = 'syn_gen:1|hd'
        Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'HD'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jun 10 14:22:31 2007
    Info: Elapsed time: 00:00:00