vh_syn.qsf

标准电视信号的同步生成程序

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		vh_syn_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:13:21  JUNE 10, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE syn_gen.vhd
set_global_assignment -name GDF_FILE vh_syn.gdf

# Pin & Location Assignments
# ==========================
set_location_assignment LC33 -to "syn_gen:1|hd"

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY vh_syn

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EPM7128SQI100-10"
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Assembler Assignments
# =====================
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFF
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0.0ns
set_global_assignment -name GLITCH_INTERVAL 0.0ns
set_global_assignment -name END_TIME 50.0ms