📄 guangshanchi.tan.qmsg

📁 光栅尺的四细分和辩向电路
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "SubDir:inst1\|36 A CLK 7.000 ns register " "Info: tsu for register \"SubDir:inst1\|36\" (data pin = \"A\", clock pin = \"CLK\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns A 1 CLK PIN_85 6 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_85; Fanout = 6; CLK Node = 'A'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { A } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 104 64 232 120 "A" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns SubDir:inst1\|36 2 REG LC42 12 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC42; Fanout = 12; REG Node = 'SubDir:inst1\|36'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { A SubDir:inst1|36 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.500 ns" { A SubDir:inst1|36 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { A A~out SubDir:inst1|36 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CLK } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 120 64 232 136 "CLK" "" } { 144 808 840 160 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns SubDir:inst1\|36 2 REG LC42 12 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC42; Fanout = 12; REG Node = 'SubDir:inst1\|36'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "0.000 ns" { CLK SubDir:inst1|36 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { -88 488 552 -8 "36" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CLK SubDir:inst1|36 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out SubDir:inst1|36 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.500 ns" { A SubDir:inst1|36 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { A A~out SubDir:inst1|36 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CLK SubDir:inst1|36 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out SubDir:inst1|36 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK cnt\[23\] CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[23\] 18.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"cnt\[23\]\" through register \"CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[23\]\" is 18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 14.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CLK } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 120 64 232 136 "CLK" "" } { 144 808 840 160 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns SubDir:inst1\|38 2 REG LC20 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC20; Fanout = 10; REG Node = 'SubDir:inst1\|38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "2.000 ns" { CLK SubDir:inst1|38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns SubDir:inst1\|8~156 3 COMB SEXP53 7 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = SEXP53; Fanout = 7; COMB Node = 'SubDir:inst1\|8~156'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { SubDir:inst1|38 SubDir:inst1|8~156 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 14.500 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[23\] 4 REG LC59 3 " "Info: 4: + IC(0.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC59; Fanout = 3; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[23\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "5.000 ns" { SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.500 ns 93.10 % " "Info: Total cell delay = 13.500 ns ( 93.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.90 % " "Info: Total interconnect delay = 1.000 ns ( 6.90 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[23\] 1 REG LC59 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 3; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[23\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns cnt\[23\] 2 PIN PIN_30 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'cnt\[23\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] cnt[23] } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 208 848 1024 224 "cnt\[23..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] cnt[23] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] cnt[23] } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~156 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "1.500 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] cnt[23] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.500 ns" { CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[23] cnt[23] } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\] SCLR CLK 11.000 ns register " "Info: th for register \"CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\]\" (data pin = \"SCLR\", clock pin = \"CLK\") is 11.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 14.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_87 12 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_87; Fanout = 12; CLK Node = 'CLK'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { CLK } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 120 64 232 136 "CLK" "" } { 144 808 840 160 "CLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 3.500 ns SubDir:inst1\|38 2 REG LC20 10 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 3.500 ns; Loc. = LC20; Fanout = 10; REG Node = 'SubDir:inst1\|38'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "2.000 ns" { CLK SubDir:inst1|38 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 64 496 560 144 "38" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 9.500 ns SubDir:inst1\|8~155 3 COMB SEXP33 8 " "Info: 3: + IC(1.000 ns) + CELL(5.000 ns) = 9.500 ns; Loc. = SEXP33; Fanout = 8; COMB Node = 'SubDir:inst1\|8~155'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { SubDir:inst1|38 SubDir:inst1|8~155 } "NODE_NAME" } "" } } { "SubDir.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/SubDir.bdf" { { 480 728 792 552 "8" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.000 ns) 14.500 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\] 4 REG LC33 51 " "Info: 4: + IC(0.000 ns) + CELL(5.000 ns) = 14.500 ns; Loc. = LC33; Fanout = 51; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "5.000 ns" { SubDir:inst1|8~155 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.500 ns 93.10 % " "Info: Total cell delay = 13.500 ns ( 93.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.90 % " "Info: Total interconnect delay = 1.000 ns ( 6.90 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~155 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~155 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SCLR 1 PIN PIN_92 81 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_92; Fanout = 81; PIN Node = 'SCLR'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "" { SCLR } "NODE_NAME" } "" } } { "GuangShanChi.bdf" "" { Schematic "D:/altera/qdesigns50/GuangShanChi/GuangShanChi.bdf" { { 40 64 232 56 "SCLR" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\] 2 REG LC33 51 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC33; Fanout = 51; REG Node = 'CntOut:inst\|lpm_counter24:inst\|lpm_counter:lpm_counter_component\|dffs\[0\]'" {  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.000 ns" { SCLR CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 84.62 % " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 15.38 % " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.500 ns" { SCLR CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { SCLR SCLR~out CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}  } { { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "14.500 ns" { CLK SubDir:inst1|38 SubDir:inst1|8~155 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.500 ns" { CLK CLK~out SubDir:inst1|38 SubDir:inst1|8~155 CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 1.500ns 2.000ns 5.000ns 5.000ns } } } { "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" "" { Report "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi_cmp.qrpt" Compiler "GuangShanChi" "UNKNOWN" "V1" "D:/altera/qdesigns50/GuangShanChi/db/GuangShanChi.quartus_db" { Floorplan "D:/altera/qdesigns50/GuangShanChi/" "" "6.500 ns" { SCLR CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.500 ns" { SCLR SCLR~out CntOut:inst|lpm_counter24:inst|lpm_counter:lpm_counter_component|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0}
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